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Commit db9825c9 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2018-09-21' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



Driver Changes:

- Bugzilla 107600: Fix stuttering video playback on MythTV on old hardware (Chris)
- Avoid black screen when using CSC coefficient matrix (Raviraj)
- Hammer PDs on Baytrail to make sure they reload (Chris)
- Capture some objects if unable to capture all, on error (Chris)
- Add W/A for 16 GB DIMMs on SKL+ (Mahesh)
- Only enable IPC for symmetric memory configurations on KBL+ (Mahesh)
- Assume pipe A to have maximum stride limits (Ville)
- Always update update OA contexts via context image (Tvrtko)
- Icelake enabling patches (Madhav, Dhinakaran)
- Add Icelake DMC firmware (Anusha)
- Fixes for CI found corner cases (Chris)
- Limit the backpressure for request allocation (Chris)
- Park GPU on module load so usage starts from known state (Chris)
- Flush tasklet when checking for idle (Chris)
- Use coherent write into the context image on BSW+ (Chris)
- Fix possible integer overflow for framebuffers that get aligned past 4GiB (Ville)
- Downgrade fence timeout from warn to notice and add debug hint (Chris)

- Fixes to multi function encoder code (Ville)
- Fix sprite plane check logic (Dan, Ville)
- PAGE_SIZE vs. I915_GTT_PAGE_SIZE fixes (Ville)
- Decode memory bandwidth and parameters for BXT and SKL+ (Mahesh)
- Overwrite BIOS set IPC value from KMS (Mahesh)
- Multiple pipe handling code cleanups/restructurings/optimizations (Ville)
- Spare low 4G address for non-48bit objects (Chris)
- Free context_setparam of struct_mutex (Chris)
- Delay updating ring register state on resume (Chris)
- Avoid unnecessarily copying overlay IOCTL parameters (Chris)
- Update GuC power domain states even without submission (Michal)
- Restore GuC preempt-context across S3/S4 (Chris)
- Add kernel selftest for rapid context switching (Chris)
- Keep runtime power management ref for live selftests (Chris)
- GEM code cleanups (Matt)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180927095933.GA11458@jlahtine-desk.ger.corp.intel.com
parents 156e60bc 44862610

drivers/gpu/drm/i915/i915_debugfs.c

+11 −0
Original line number Diff line number Diff line
@@ -4117,6 +4117,17 @@ i915_ring_test_irq_set(void *data, u64 val) 
{

	struct drm_i915_private *i915 = data;



	/* GuC keeps the user interrupt permanently enabled for submission */

	if (USES_GUC_SUBMISSION(i915))

		return -ENODEV;



	/*

	 * From icl, we can no longer individually mask interrupt generation

	 * from each engine.

	 */

	if (INTEL_GEN(i915) >= 11)

		return -ENODEV;



	val &= INTEL_INFO(i915)->ring_mask;

	DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);

drivers/gpu/drm/i915/i915_drv.c

+300 −0
Original line number Diff line number Diff line
@@ -1063,6 +1063,300 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv) 
	intel_gvt_sanitize_options(dev_priv);

}



static enum dram_rank skl_get_dimm_rank(u8 size, u32 rank)

{

	if (size == 0)

		return I915_DRAM_RANK_INVALID;

	if (rank == SKL_DRAM_RANK_SINGLE)

		return I915_DRAM_RANK_SINGLE;

	else if (rank == SKL_DRAM_RANK_DUAL)

		return I915_DRAM_RANK_DUAL;



	return I915_DRAM_RANK_INVALID;

}



static bool

skl_is_16gb_dimm(enum dram_rank rank, u8 size, u8 width)

{

	if (rank == I915_DRAM_RANK_SINGLE && width == 8 && size == 16)

		return true;

	else if (rank == I915_DRAM_RANK_DUAL && width == 8 && size == 32)

		return true;

	else if (rank == SKL_DRAM_RANK_SINGLE && width == 16 && size == 8)

		return true;

	else if (rank == SKL_DRAM_RANK_DUAL && width == 16 && size == 16)

		return true;



	return false;

}



static int

skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)

{

	u32 tmp_l, tmp_s;

	u32 s_val = val >> SKL_DRAM_S_SHIFT;



	if (!val)

		return -EINVAL;



	tmp_l = val & SKL_DRAM_SIZE_MASK;

	tmp_s = s_val & SKL_DRAM_SIZE_MASK;



	if (tmp_l == 0 && tmp_s == 0)

		return -EINVAL;



	ch->l_info.size = tmp_l;

	ch->s_info.size = tmp_s;



	tmp_l = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;

	tmp_s = (s_val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;

	ch->l_info.width = (1 << tmp_l) * 8;

	ch->s_info.width = (1 << tmp_s) * 8;



	tmp_l = val & SKL_DRAM_RANK_MASK;

	tmp_s = s_val & SKL_DRAM_RANK_MASK;

	ch->l_info.rank = skl_get_dimm_rank(ch->l_info.size, tmp_l);

	ch->s_info.rank = skl_get_dimm_rank(ch->s_info.size, tmp_s);



	if (ch->l_info.rank == I915_DRAM_RANK_DUAL ||

	    ch->s_info.rank == I915_DRAM_RANK_DUAL)

		ch->rank = I915_DRAM_RANK_DUAL;

	else if (ch->l_info.rank == I915_DRAM_RANK_SINGLE &&

		 ch->s_info.rank == I915_DRAM_RANK_SINGLE)

		ch->rank = I915_DRAM_RANK_DUAL;

	else

		ch->rank = I915_DRAM_RANK_SINGLE;



	ch->is_16gb_dimm = skl_is_16gb_dimm(ch->l_info.rank, ch->l_info.size,

					    ch->l_info.width) ||

			   skl_is_16gb_dimm(ch->s_info.rank, ch->s_info.size,

					    ch->s_info.width);



	DRM_DEBUG_KMS("(size:width:rank) L(%dGB:X%d:%s) S(%dGB:X%d:%s)\n",

		      ch->l_info.size, ch->l_info.width,

		      ch->l_info.rank ? "dual" : "single",

		      ch->s_info.size, ch->s_info.width,

		      ch->s_info.rank ? "dual" : "single");



	return 0;

}



static bool

intel_is_dram_symmetric(u32 val_ch0, u32 val_ch1,

			struct dram_channel_info *ch0)

{

	return (val_ch0 == val_ch1 &&

		(ch0->s_info.size == 0 ||

		 (ch0->l_info.size == ch0->s_info.size &&

		  ch0->l_info.width == ch0->s_info.width &&

		  ch0->l_info.rank == ch0->s_info.rank)));

}



static int

skl_dram_get_channels_info(struct drm_i915_private *dev_priv)

{

	struct dram_info *dram_info = &dev_priv->dram_info;

	struct dram_channel_info ch0, ch1;

	u32 val_ch0, val_ch1;

	int ret;



	val_ch0 = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);

	ret = skl_dram_get_channel_info(&ch0, val_ch0);

	if (ret == 0)

		dram_info->num_channels++;



	val_ch1 = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);

	ret = skl_dram_get_channel_info(&ch1, val_ch1);

	if (ret == 0)

		dram_info->num_channels++;



	if (dram_info->num_channels == 0) {

		DRM_INFO("Number of memory channels is zero\n");

		return -EINVAL;

	}



	dram_info->valid_dimm = true;



	/*

	 * If any of the channel is single rank channel, worst case output

	 * will be same as if single rank memory, so consider single rank

	 * memory.

	 */

	if (ch0.rank == I915_DRAM_RANK_SINGLE ||

	    ch1.rank == I915_DRAM_RANK_SINGLE)

		dram_info->rank = I915_DRAM_RANK_SINGLE;

	else

		dram_info->rank = max(ch0.rank, ch1.rank);



	if (dram_info->rank == I915_DRAM_RANK_INVALID) {

		DRM_INFO("couldn't get memory rank information\n");

		return -EINVAL;

	}



	if (ch0.is_16gb_dimm || ch1.is_16gb_dimm)

		dram_info->is_16gb_dimm = true;



	dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,

								       val_ch1,

								       &ch0);



	DRM_DEBUG_KMS("memory configuration is %sSymmetric memory\n",

		      dev_priv->dram_info.symmetric_memory ? "" : "not ");

	return 0;

}



static int

skl_get_dram_info(struct drm_i915_private *dev_priv)

{

	struct dram_info *dram_info = &dev_priv->dram_info;

	u32 mem_freq_khz, val;

	int ret;



	ret = skl_dram_get_channels_info(dev_priv);

	if (ret)

		return ret;



	val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);

	mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *

				    SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);



	dram_info->bandwidth_kbps = dram_info->num_channels *

							mem_freq_khz * 8;



	if (dram_info->bandwidth_kbps == 0) {

		DRM_INFO("Couldn't get system memory bandwidth\n");

		return -EINVAL;

	}



	dram_info->valid = true;

	return 0;

}



static int

bxt_get_dram_info(struct drm_i915_private *dev_priv)

{

	struct dram_info *dram_info = &dev_priv->dram_info;

	u32 dram_channels;

	u32 mem_freq_khz, val;

	u8 num_active_channels;

	int i;



	val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);

	mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *

				    BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);



	dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;

	num_active_channels = hweight32(dram_channels);



	/* Each active bit represents 4-byte channel */

	dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);



	if (dram_info->bandwidth_kbps == 0) {

		DRM_INFO("Couldn't get system memory bandwidth\n");

		return -EINVAL;

	}



	/*

	 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.

	 */

	for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {

		u8 size, width;

		enum dram_rank rank;

		u32 tmp;



		val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));

		if (val == 0xFFFFFFFF)

			continue;



		dram_info->num_channels++;

		tmp = val & BXT_DRAM_RANK_MASK;



		if (tmp == BXT_DRAM_RANK_SINGLE)

			rank = I915_DRAM_RANK_SINGLE;

		else if (tmp == BXT_DRAM_RANK_DUAL)

			rank = I915_DRAM_RANK_DUAL;

		else

			rank = I915_DRAM_RANK_INVALID;



		tmp = val & BXT_DRAM_SIZE_MASK;

		if (tmp == BXT_DRAM_SIZE_4GB)

			size = 4;

		else if (tmp == BXT_DRAM_SIZE_6GB)

			size = 6;

		else if (tmp == BXT_DRAM_SIZE_8GB)

			size = 8;

		else if (tmp == BXT_DRAM_SIZE_12GB)

			size = 12;

		else if (tmp == BXT_DRAM_SIZE_16GB)

			size = 16;

		else

			size = 0;



		tmp = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;

		width = (1 << tmp) * 8;

		DRM_DEBUG_KMS("dram size:%dGB width:X%d rank:%s\n", size,

			      width, rank == I915_DRAM_RANK_SINGLE ? "single" :

			      rank == I915_DRAM_RANK_DUAL ? "dual" : "unknown");



		/*

		 * If any of the channel is single rank channel,

		 * worst case output will be same as if single rank

		 * memory, so consider single rank memory.

		 */

		if (dram_info->rank == I915_DRAM_RANK_INVALID)

			dram_info->rank = rank;

		else if (rank == I915_DRAM_RANK_SINGLE)

			dram_info->rank = I915_DRAM_RANK_SINGLE;

	}



	if (dram_info->rank == I915_DRAM_RANK_INVALID) {

		DRM_INFO("couldn't get memory rank information\n");

		return -EINVAL;

	}



	dram_info->valid_dimm = true;

	dram_info->valid = true;

	return 0;

}



static void

intel_get_dram_info(struct drm_i915_private *dev_priv)

{

	struct dram_info *dram_info = &dev_priv->dram_info;

	char bandwidth_str[32];

	int ret;



	dram_info->valid = false;

	dram_info->valid_dimm = false;

	dram_info->is_16gb_dimm = false;

	dram_info->rank = I915_DRAM_RANK_INVALID;

	dram_info->bandwidth_kbps = 0;

	dram_info->num_channels = 0;



	if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))

		return;



	/* Need to calculate bandwidth only for Gen9 */

	if (IS_BROXTON(dev_priv))

		ret = bxt_get_dram_info(dev_priv);

	else if (INTEL_GEN(dev_priv) == 9)

		ret = skl_get_dram_info(dev_priv);

	else

		ret = skl_dram_get_channels_info(dev_priv);

	if (ret)

		return;



	if (dram_info->bandwidth_kbps)

		sprintf(bandwidth_str, "%d KBps", dram_info->bandwidth_kbps);

	else

		sprintf(bandwidth_str, "unknown");

	DRM_DEBUG_KMS("DRAM bandwidth:%s, total-channels: %u\n",

		      bandwidth_str, dram_info->num_channels);

	DRM_DEBUG_KMS("DRAM rank: %s rank 16GB-dimm:%s\n",

		      (dram_info->rank == I915_DRAM_RANK_DUAL) ?

		      "dual" : "single", yesno(dram_info->is_16gb_dimm));

}



/**

 * i915_driver_init_hw - setup state requiring device access

 * @dev_priv: device private
@@ -1180,6 +1474,12 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) 
		goto err_msi;



	intel_opregion_setup(dev_priv);

	/*

	 * Fill the dram structure to get the system raw bandwidth and

	 * dram info. This will be used for memory latency calculation.

	 */

	intel_get_dram_info(dev_priv);





	return 0;

drivers/gpu/drm/i915/i915_drv.h

+33 −4
Original line number Diff line number Diff line
@@ -87,8 +87,8 @@ 


#define DRIVER_NAME		"i915"

#define DRIVER_DESC		"Intel Graphics"

#define DRIVER_DATE		"20180906"

#define DRIVER_TIMESTAMP	1536242083

#define DRIVER_DATE		"20180921"

#define DRIVER_TIMESTAMP	1537521997



/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and

 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
@@ -1946,6 +1946,20 @@ struct drm_i915_private { 
		bool distrust_bios_wm;

	} wm;



	struct dram_info {

		bool valid;

		bool valid_dimm;

		bool is_16gb_dimm;

		u8 num_channels;

		enum dram_rank {

			I915_DRAM_RANK_INVALID = 0,

			I915_DRAM_RANK_SINGLE,

			I915_DRAM_RANK_DUAL

		} rank;

		u32 bandwidth_kbps;

		bool symmetric_memory;

	} dram_info;



	struct i915_runtime_pm runtime_pm;



	struct {
@@ -2159,6 +2173,15 @@ struct drm_i915_private { 
	 */

};



struct dram_channel_info {

	struct info {

		u8 size, width;

		enum dram_rank rank;

	} l_info, s_info;

	enum dram_rank rank;

	bool is_16gb_dimm;

};



static inline struct drm_i915_private *to_i915(const struct drm_device *dev)

{

	return container_of(dev, struct drm_i915_private, drm);
@@ -2284,7 +2307,7 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg) 
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\

	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\

	     ((__dmap) = (__iter).dma + (__iter).curr);			\

	     (((__iter).curr += PAGE_SIZE) >= (__iter).max) ?		\

	     (((__iter).curr += I915_GTT_PAGE_SIZE) >= (__iter).max) ?	\

	     (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)



/**
@@ -3074,6 +3097,12 @@ enum i915_map_type { 
	I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,

};



static inline enum i915_map_type

i915_coherent_map_type(struct drm_i915_private *i915)

{

	return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;

}



/**

 * i915_gem_object_pin_map - return a contiguous mapping of the entire object

 * @obj: the object to map into kernel address space
@@ -3311,7 +3340,7 @@ int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, 
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,

				 struct drm_mm_node *node);

int i915_gem_init_stolen(struct drm_i915_private *dev_priv);

void i915_gem_cleanup_stolen(struct drm_device *dev);

void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv);

struct drm_i915_gem_object *

i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,

			      resource_size_t size);

drivers/gpu/drm/i915/i915_gem.c

+27 −1
Original line number Diff line number Diff line
@@ -2506,7 +2506,9 @@ static bool i915_sg_trim(struct sg_table *orig_st) 
	new_sg = new_st.sgl;

	for_each_sg(orig_st->sgl, sg, orig_st->nents, i) {

		sg_set_page(new_sg, sg_page(sg), sg->length, 0);

		/* called before being DMA mapped, no need to copy sg->dma_* */

		sg_dma_address(new_sg) = sg_dma_address(sg);

		sg_dma_len(new_sg) = sg_dma_len(sg);



		new_sg = sg_next(new_sg);

	}

	GEM_BUG_ON(new_sg); /* Should walk exactly nents and hit the end */
@@ -3438,6 +3440,9 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915) 
	i915_retire_requests(i915);

	GEM_BUG_ON(i915->gt.active_requests);



	if (!intel_gpu_reset(i915, ALL_ENGINES))

		intel_engines_sanitize(i915);



	/*

	 * Undo nop_submit_request. We prevent all new i915 requests from

	 * being queued (by disallowing execbuf whilst wedged) so having
@@ -5414,8 +5419,19 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915) 


	assert_kernel_context_is_current(i915);



	/*

	 * Immediately park the GPU so that we enable powersaving and

	 * treat it as idle. The next time we issue a request, we will

	 * unpark and start using the engine->pinned_default_state, otherwise

	 * it is in limbo and an early reset may fail.

	 */

	__i915_gem_park(i915);



	for_each_engine(engine, i915, id) {

		struct i915_vma *state;

		void *vaddr;



		GEM_BUG_ON(to_intel_context(ctx, engine)->pin_count);



		state = to_intel_context(ctx, engine)->state;

		if (!state)
@@ -5438,6 +5454,16 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915) 
			goto err_active;



		engine->default_state = i915_gem_object_get(state->obj);



		/* Check we can acquire the image of the context state */

		vaddr = i915_gem_object_pin_map(engine->default_state,

						I915_MAP_FORCE_WB);

		if (IS_ERR(vaddr)) {

			err = PTR_ERR(vaddr);

			goto err_active;

		}



		i915_gem_object_unpin_map(engine->default_state);

	}



	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {

drivers/gpu/drm/i915/i915_gem_context.c

+7 −13
Original line number Diff line number Diff line
@@ -862,7 +862,7 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, 
		ret = -EINVAL;

		break;

	case I915_CONTEXT_PARAM_NO_ZEROMAP:

		args->value = ctx->flags & CONTEXT_NO_ZEROMAP;

		args->value = test_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags);

		break;

	case I915_CONTEXT_PARAM_GTT_SIZE:

		if (ctx->ppgtt)
@@ -896,27 +896,23 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, 
	struct drm_i915_file_private *file_priv = file->driver_priv;

	struct drm_i915_gem_context_param *args = data;

	struct i915_gem_context *ctx;

	int ret;

	int ret = 0;



	ctx = i915_gem_context_lookup(file_priv, args->ctx_id);

	if (!ctx)

		return -ENOENT;



	ret = i915_mutex_lock_interruptible(dev);

	if (ret)

		goto out;



	switch (args->param) {

	case I915_CONTEXT_PARAM_BAN_PERIOD:

		ret = -EINVAL;

		break;

	case I915_CONTEXT_PARAM_NO_ZEROMAP:

		if (args->size) {

		if (args->size)

			ret = -EINVAL;

		} else {

			ctx->flags &= ~CONTEXT_NO_ZEROMAP;

			ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;

		}

		else if (args->value)

			set_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags);

		else

			clear_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags);

		break;

	case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:

		if (args->size)
@@ -960,9 +956,7 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, 
		ret = -EINVAL;

		break;

	}

	mutex_unlock(&dev->struct_mutex);



out:

	i915_gem_context_put(ctx);

	return ret;

}