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Commit db6668d8 authored by Kuninori Morimoto's avatar Kuninori Morimoto Committed by Florian Tobias Schandinat
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fbdev: sh_mobile_hdmi: 32bit register access support 



Latest SuperH HDMI allows 32bit access only.
But the data is 8bit. So, we can keep compatibility by switching 8/32 bit access.

Signed-off-by: default avatarKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: default avatarFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>
parent e0defc86

drivers/video/sh_mobile_hdmi.c

+36 −2
Original line number Original line Diff line number Diff line
@@ -222,20 +222,45 @@ struct sh_hdmi { 
	struct delayed_work edid_work;

	struct delayed_work edid_work;

	struct fb_videomode mode;

	struct fb_videomode mode;

	struct fb_monspecs monspec;

	struct fb_monspecs monspec;



	/* register access functions */

	void (*write)(struct sh_hdmi *hdmi, u8 data, u8 reg);

	u8 (*read)(struct sh_hdmi *hdmi, u8 reg);

};

};





#define entity_to_sh_hdmi(e)	container_of(e, struct sh_hdmi, entity)

#define entity_to_sh_hdmi(e)	container_of(e, struct sh_hdmi, entity)





static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)

static void __hdmi_write8(struct sh_hdmi *hdmi, u8 data, u8 reg)

{

{

	iowrite8(data, hdmi->base + reg);

	iowrite8(data, hdmi->base + reg);

}

}





static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)

static u8 __hdmi_read8(struct sh_hdmi *hdmi, u8 reg)

{

{

	return ioread8(hdmi->base + reg);

	return ioread8(hdmi->base + reg);

}

}





static void __hdmi_write32(struct sh_hdmi *hdmi, u8 data, u8 reg)

{

	iowrite32((u32)data, hdmi->base + (reg * 4));

	udelay(100);

}



static u8 __hdmi_read32(struct sh_hdmi *hdmi, u8 reg)

{

	return (u8)ioread32(hdmi->base + (reg * 4));

}



static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)

{

	hdmi->write(hdmi, data, reg);

}



static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)

{

	return hdmi->read(hdmi, reg);

}



static void hdmi_bit_set(struct sh_hdmi *hdmi, u8 mask, u8 data, u8 reg)

static void hdmi_bit_set(struct sh_hdmi *hdmi, u8 mask, u8 data, u8 reg)

{

{

	u8 val = hdmi_read(hdmi, reg);

	u8 val = hdmi_read(hdmi, reg);
@@ -1148,6 +1173,15 @@ static int __init sh_hdmi_probe(struct platform_device *pdev) 
		goto egetclk;

		goto egetclk;

	}

	}





	/* select register access functions */

	if (pdata->flags & HDMI_32BIT_REG) {

		hdmi->write	= __hdmi_write32;

		hdmi->read	= __hdmi_read32;

	} else {

		hdmi->write	= __hdmi_write8;

		hdmi->read	= __hdmi_read8;

	}



	/* An arbitrary relaxed pixclock just to get things started: from standard 480p */

	/* An arbitrary relaxed pixclock just to get things started: from standard 480p */

	rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));

	rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));

	if (rate > 0)

	if (rate > 0)

include/video/sh_mobile_hdmi.h

+4 −1
Original line number Original line Diff line number Diff line
@@ -18,10 +18,11 @@ struct clk; 
/*

/*

 * flags format

 * flags format

 *

 *

 * 0x000000BA

 * 0x00000CBA

 *

 *

 * A: Audio source select

 * A: Audio source select

 * B: Int output option

 * B: Int output option

 * C: Chip specific option

 */

 */





/* Audio source select */

/* Audio source select */
@@ -35,6 +36,8 @@ struct clk; 
#define HDMI_OUTPUT_PUSH_PULL	(1 << 4) /* System control : output mode */

#define HDMI_OUTPUT_PUSH_PULL	(1 << 4) /* System control : output mode */

#define HDMI_OUTPUT_POLARITY_HI	(1 << 5) /* System control : output polarity */

#define HDMI_OUTPUT_POLARITY_HI	(1 << 5) /* System control : output polarity */





/* Chip specific option */

#define HDMI_32BIT_REG		(1 << 8)





struct sh_mobile_hdmi_info {

struct sh_mobile_hdmi_info {

	unsigned int			 flags;

	unsigned int			 flags;