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Commit db64a2f4 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: fix possible hang with 3+ 4K monitors 



If DAL requires to force MCLK high, the FCLK will be
forced to high also.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent aaaba51b

drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

+9 −1
Original line number Diff line number Diff line
@@ -3470,6 +3470,7 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) 
	struct vega20_single_dpm_table *dpm_table;

	bool vblank_too_short = false;

	bool disable_mclk_switching;

	bool disable_fclk_switching;

	uint32_t i, latency;



	disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
@@ -3545,13 +3546,20 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) 
	if (hwmgr->display_config->nb_pstate_switch_disable)

		dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;



	if ((disable_mclk_switching &&

	    (dpm_table->dpm_state.hard_min_level == dpm_table->dpm_levels[dpm_table->count - 1].value)) ||

	     hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].value)

		disable_fclk_switching = true;

	else

		disable_fclk_switching = false;



	/* fclk */

	dpm_table = &(data->dpm_table.fclk_table);

	dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;

	dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;

	dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;

	dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;

	if (hwmgr->display_config->nb_pstate_switch_disable)

	if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching)

		dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;



	/* vclk */