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Commit db3db807 authored by Sarthak Garg's avatar Sarthak Garg Committed by Gerrit - the friendly Code Review server
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mmc: sdhci-msm: Avoid overiding of vendor_specific_func register 



For HS400 tuning in HS200 mode MCLK should be configured to 384 MHz in GCC.
The clock on the bus should be 192MHz which is achieved by selecting MCLK/2
in VENDOR_SPECIFIC_FUNC by setting SDC4_MCLK_SEL field values as 3.

But the above register configurations are getting overridden with older
values leading to tuning failure for HS400 mode.

Avoid overiding of vendor_specific_func register.

Change-Id: I8ff094f6fa5019a0b42ed9716e52b9fd9c085934
Signed-off-by: default avatarSarthak Garg <sartgarg@codeaurora.org>
parent 774e9013

drivers/mmc/host/sdhci-msm.c

+3 −3
Original line number Diff line number Diff line
@@ -1495,9 +1495,6 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode) 
	const struct sdhci_msm_offset *msm_offset =

					sdhci_priv_msm_offset(host);



	core_vendor_spec = readl_relaxed(host->ioaddr +

			msm_offset->core_vendor_spec);



	if (!sdhci_msm_is_tuning_needed(host)) {

		msm_host->use_cdr = false;

		sdhci_msm_set_cdr(host, false);
@@ -1524,6 +1521,9 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode) 
		host->flags &= ~SDHCI_HS400_TUNING;

	}



	core_vendor_spec = readl_relaxed(host->ioaddr +

			msm_offset->core_vendor_spec);



	/* Make sure that PWRSAVE bit is set to '0' during tuning */

	writel_relaxed((core_vendor_spec & ~CORE_CLK_PWRSAVE),

			host->ioaddr +