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Commit dafef683 authored by Jack Pham's avatar Jack Pham
Browse files

ARM: dts: msm: Update USB3 DP QMP Phy sequence for Lahaina to v1.10 

Update the QMP USB3 DP PHY init sequence to v1.10 of the HSR. This
is a minor update with only two register updates which addresses
USB SuperSpeedPlus Gen2 RX compliance testing.

Change-Id: I1f4de5c2657bb65861c94eadcde83a2cbe9be9ef
parent 840b38c0

qcom/lahaina-usb.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -232,7 +232,7 @@ 
			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0

			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21 0

			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x0A 0

			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0

			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x03 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0

			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
@@ -278,7 +278,7 @@ 
			USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F 0

			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0

			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x21 0

			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0

			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x03 0

			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x0A 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0

			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0