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Commit da1043cf authored by Eric Bernstein's avatar Eric Bernstein Committed by Alex Deucher
Browse files

drm/amd/display: Fix runtime errors for diagnostic tests 



1) Rename and make public definition of input CSC matrix struct.
2) Make wm_read_state() function an interface of hubbub, and check
   if watermark registers exist before read/write to them.
3) Check if OTG_INTERLACE_CONTROL register exists before updating
4) Add dummy functions for set_input/output_transfer function to avoid
   errors due to differences in CM registers.
5) Added missing register field definition in header file

Signed-off-by: default avatarEric Bernstein <eric.bernstein@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 60a804c8

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

+4 −8
Original line number Diff line number Diff line
@@ -51,10 +51,6 @@ 


#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))



struct dcn10_input_csc_matrix {

	enum dc_color_space color_space;

	uint16_t regval[12];

};



enum dcn10_coef_filter_type_sel {

	SCL_COEF_LUMA_VERT_FILTER = 0,
@@ -99,7 +95,7 @@ enum gamut_remap_select { 
	GAMUT_REMAP_COMB_COEFF

};



static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = {

static const struct dpp_input_csc_matrix dpp_input_csc_matrix[] = {

	{COLOR_SPACE_SRGB,

		{0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },

	{COLOR_SPACE_SRGB_LIMITED,
@@ -454,7 +450,7 @@ void dpp1_program_input_csc( 
{

	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

	int i;

	int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);

	int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix);

	const uint16_t *regval = NULL;

	uint32_t cur_select = 0;

	enum dcn10_input_csc_select select;
@@ -467,8 +463,8 @@ void dpp1_program_input_csc( 


	if (tbl_entry == NULL) {

		for (i = 0; i < arr_size; i++)

			if (dcn10_input_csc_matrix[i].color_space == color_space) {

				regval = dcn10_input_csc_matrix[i].regval;

			if (dpp_input_csc_matrix[i].color_space == color_space) {

				regval = dpp_input_csc_matrix[i].regval;

				break;

			}

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c

+41 −32
Original line number Diff line number Diff line
@@ -275,6 +275,7 @@ void hubbub1_program_watermarks( 
			watermarks->a.urgent_ns, prog_wm_value);

	}



	if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A)) {

		if (safe_to_lower || watermarks->a.pte_meta_urgent_ns > hubbub->watermarks.a.pte_meta_urgent_ns) {

			hubbub->watermarks.a.pte_meta_urgent_ns = watermarks->a.pte_meta_urgent_ns;

			prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
@@ -284,6 +285,7 @@ void hubbub1_program_watermarks( 
				"HW register value = 0x%x\n",

				watermarks->a.pte_meta_urgent_ns, prog_wm_value);

		}

	}



	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {

		if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
@@ -338,6 +340,7 @@ void hubbub1_program_watermarks( 
			watermarks->b.urgent_ns, prog_wm_value);

	}



	if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B)) {

		if (safe_to_lower || watermarks->b.pte_meta_urgent_ns > hubbub->watermarks.b.pte_meta_urgent_ns) {

			hubbub->watermarks.b.pte_meta_urgent_ns = watermarks->b.pte_meta_urgent_ns;

			prog_wm_value = convert_and_clamp(watermarks->b.pte_meta_urgent_ns,
@@ -347,6 +350,7 @@ void hubbub1_program_watermarks( 
				"HW register value = 0x%x\n",

				watermarks->b.pte_meta_urgent_ns, prog_wm_value);

		}

	}



	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {

		if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
@@ -401,6 +405,7 @@ void hubbub1_program_watermarks( 
			watermarks->c.urgent_ns, prog_wm_value);

	}



	if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C)) {

		if (safe_to_lower || watermarks->c.pte_meta_urgent_ns > hubbub->watermarks.c.pte_meta_urgent_ns) {

			hubbub->watermarks.c.pte_meta_urgent_ns = watermarks->c.pte_meta_urgent_ns;

			prog_wm_value = convert_and_clamp(watermarks->c.pte_meta_urgent_ns,
@@ -410,6 +415,7 @@ void hubbub1_program_watermarks( 
				"HW register value = 0x%x\n",

				watermarks->c.pte_meta_urgent_ns, prog_wm_value);

		}

	}



	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {

		if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
@@ -464,6 +470,7 @@ void hubbub1_program_watermarks( 
			watermarks->d.urgent_ns, prog_wm_value);

	}



	if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D)) {

		if (safe_to_lower || watermarks->d.pte_meta_urgent_ns > hubbub->watermarks.d.pte_meta_urgent_ns) {

			hubbub->watermarks.d.pte_meta_urgent_ns = watermarks->d.pte_meta_urgent_ns;

			prog_wm_value = convert_and_clamp(watermarks->d.pte_meta_urgent_ns,
@@ -473,6 +480,7 @@ void hubbub1_program_watermarks( 
				"HW register value = 0x%x\n",

				watermarks->d.pte_meta_urgent_ns, prog_wm_value);

		}

	}



	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {

		if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
@@ -837,6 +845,7 @@ static const struct hubbub_funcs hubbub1_funcs = { 
	.dcc_support_swizzle = hubbub1_dcc_support_swizzle,

	.dcc_support_pixel_format = hubbub1_dcc_support_pixel_format,

	.get_dcc_compression_cap = hubbub1_get_dcc_compression_cap,

	.wm_read_state = hubbub1_wm_read_state,

};



void hubbub1_construct(struct hubbub *hubbub,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h

+0 −12
Original line number Diff line number Diff line
@@ -165,18 +165,6 @@ struct dcn_hubbub_mask { 


struct dc;



struct dcn_hubbub_wm_set {

	uint32_t wm_set;

	uint32_t data_urgent;

	uint32_t pte_meta_urgent;

	uint32_t sr_enter;

	uint32_t sr_exit;

	uint32_t dram_clk_chanage;

};



struct dcn_hubbub_wm {

	struct dcn_hubbub_wm_set sets[4];

};



struct hubbub {

	const struct hubbub_funcs *funcs;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+1 −1
Original line number Diff line number Diff line
@@ -95,7 +95,7 @@ void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx) 
	struct dcn_hubbub_wm wm = {0};

	int i;



	hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);

	dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);



	DTN_INFO("HUBBUB WM:      data_urgent  pte_meta_urgent"

			"         sr_enter          sr_exit  dram_clk_change\n");

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

+1 −1
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ static unsigned int dcn10_get_hubbub_state(struct dc *dc, char *pBuf, unsigned i 
	const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 1000;

	static const unsigned int frac = 1000;



	hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);

	dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);



	chars_printed = snprintf_count(pBuf, remaining_buffer, "wm_set_index,data_urgent,pte_meta_urgent,sr_enter,sr_exit,dram_clk_chanage\n");

	remaining_buffer -= chars_printed;