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Commit d95eabc7 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-dt-fixes-for-v4.8' of...

Merge tag 'renesas-dt-fixes-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Merge "Renesas ARM Based SoC DT Fixes for v4.8" from Simon Horman:

* Corrections to r8a7792

* tag 'renesas-dt-fixes-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: dts: r8a7792: remove ADSP clock
  ARM: dts: r8a7792: add PLL1 divided by 2 clock
parents 1b2d8b94 e0c3f92a
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+8 −1
Original line number Original line Diff line number Diff line
@@ -279,11 +279,18 @@
			clocks = <&extal_clk>;
			clocks = <&extal_clk>;
			#clock-cells = <1>;
			#clock-cells = <1>;
			clock-output-names = "main", "pll0", "pll1", "pll3",
			clock-output-names = "main", "pll0", "pll1", "pll3",
					     "lb", "qspi", "z", "adsp";
					     "lb", "qspi", "z";
			#power-domain-cells = <0>;
			#power-domain-cells = <0>;
		};
		};


		/* Fixed factor clocks */
		/* Fixed factor clocks */
		pll1_div2_clk: pll1_div2 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
		};
		zs_clk: zs {
		zs_clk: zs {
			compatible = "fixed-factor-clock";
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+0 −1
Original line number Original line Diff line number Diff line
@@ -18,7 +18,6 @@
#define R8A7792_CLK_LB			4
#define R8A7792_CLK_LB			4
#define R8A7792_CLK_QSPI		5
#define R8A7792_CLK_QSPI		5
#define R8A7792_CLK_Z			6
#define R8A7792_CLK_Z			6
#define R8A7792_CLK_ADSP		7


/* MSTP0 */
/* MSTP0 */
#define R8A7792_CLK_MSIOF0		0
#define R8A7792_CLK_MSIOF0		0