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Commit d930ac79 authored by Aya Levin's avatar Aya Levin Committed by Saeed Mahameed
Browse files

net/mlx5e: Refactor TIR configuration function 



Refactor mlx5e_build_indir_tir_ctx_hash for better code re-use. TIR
stands for Transport Interface Receive, which is responsible for all
transport related operations on the receive side. Added a
static array with TIR default configuration values. This separates
configuration values from command setting, which is needed for
downstream patch.

Signed-off-by: default avatarAya Levin <ayal@mellanox.com>
Reviewed-by: default avatarTariq Toukan <tariqt@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent 080d1b17

drivers/net/ethernet/mellanox/mlx5/core/en.h

+2 −1
Original line number Diff line number Diff line
@@ -797,9 +797,10 @@ struct mlx5e_redirect_rqt_param { 
int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,

		       struct mlx5e_redirect_rqt_param rrp);

void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,

				    enum mlx5e_traffic_types tt,

				    const struct mlx5e_tirc_config *ttconfig,

				    void *tirc, bool inner);

void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen);

struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt);



int mlx5e_open_locked(struct net_device *netdev);

int mlx5e_close_locked(struct net_device *netdev);

drivers/net/ethernet/mellanox/mlx5/core/en/fs.h

+16 −0
Original line number Diff line number Diff line
@@ -73,6 +73,22 @@ enum mlx5e_traffic_types { 
	MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,

};



struct mlx5e_tirc_config {

	u8 l3_prot_type;

	u8 l4_prot_type;

	u32 rx_hash_fields;

};



#define MLX5_HASH_IP		(MLX5_HASH_FIELD_SEL_SRC_IP   |\

				 MLX5_HASH_FIELD_SEL_DST_IP)

#define MLX5_HASH_IP_L4PORTS	(MLX5_HASH_FIELD_SEL_SRC_IP   |\

				 MLX5_HASH_FIELD_SEL_DST_IP   |\

				 MLX5_HASH_FIELD_SEL_L4_SPORT |\

				 MLX5_HASH_FIELD_SEL_L4_DPORT)

#define MLX5_HASH_IP_IPSEC_SPI	(MLX5_HASH_FIELD_SEL_SRC_IP   |\

				 MLX5_HASH_FIELD_SEL_DST_IP   |\

				 MLX5_HASH_FIELD_SEL_IPSEC_SPI)



enum mlx5e_tunnel_types {

	MLX5E_TT_IPV4_GRE,

	MLX5E_TT_IPV6_GRE,

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

+66 −101
Original line number Diff line number Diff line
@@ -2607,6 +2607,54 @@ static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv) 
	mlx5e_redirect_rqts(priv, drop_rrp);

}



static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {

	[MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,

				.l4_prot_type = MLX5_L4_PROT_TYPE_TCP,

				.rx_hash_fields = MLX5_HASH_IP_L4PORTS,

	},

	[MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,

				.l4_prot_type = MLX5_L4_PROT_TYPE_TCP,

				.rx_hash_fields = MLX5_HASH_IP_L4PORTS,

	},

	[MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,

				.l4_prot_type = MLX5_L4_PROT_TYPE_UDP,

				.rx_hash_fields = MLX5_HASH_IP_L4PORTS,

	},

	[MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,

				.l4_prot_type = MLX5_L4_PROT_TYPE_UDP,

				.rx_hash_fields = MLX5_HASH_IP_L4PORTS,

	},

	[MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,

				     .l4_prot_type = 0,

				     .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,

	},

	[MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,

				     .l4_prot_type = 0,

				     .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,

	},

	[MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,

				      .l4_prot_type = 0,

				      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,

	},

	[MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,

				      .l4_prot_type = 0,

				      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,

	},

	[MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,

			    .l4_prot_type = 0,

			    .rx_hash_fields = MLX5_HASH_IP,

	},

	[MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,

			    .l4_prot_type = 0,

			    .rx_hash_fields = MLX5_HASH_IP,

	},

};



struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)

{

	return tirc_default_config[tt];

}



static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)

{

	if (!params->lro_en)
@@ -2623,24 +2671,12 @@ static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc) 
}



void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,

				    enum mlx5e_traffic_types tt,

				    const struct mlx5e_tirc_config *ttconfig,

				    void *tirc, bool inner)

{

	void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :

			     MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);



#define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\

				 MLX5_HASH_FIELD_SEL_DST_IP)



#define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\

				 MLX5_HASH_FIELD_SEL_DST_IP   |\

				 MLX5_HASH_FIELD_SEL_L4_SPORT |\

				 MLX5_HASH_FIELD_SEL_L4_DPORT)



#define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\

				 MLX5_HASH_FIELD_SEL_DST_IP   |\

				 MLX5_HASH_FIELD_SEL_IPSEC_SPI)



	MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));

	if (params->rss_hfunc == ETH_RSS_HASH_TOP) {

		void *rss_key = MLX5_ADDR_OF(tirc, tirc,
@@ -2651,88 +2687,12 @@ void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params, 
		MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);

		memcpy(rss_key, params->toeplitz_hash_key, len);

	}



	switch (tt) {

	case MLX5E_TT_IPV4_TCP:

		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,

			 MLX5_L3_PROT_TYPE_IPV4);

		MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,

			 MLX5_L4_PROT_TYPE_TCP);

		MLX5_SET(rx_hash_field_select, hfso, selected_fields,

			 MLX5_HASH_IP_L4PORTS);

		break;



	case MLX5E_TT_IPV6_TCP:

		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,

			 MLX5_L3_PROT_TYPE_IPV6);

		MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,

			 MLX5_L4_PROT_TYPE_TCP);

		MLX5_SET(rx_hash_field_select, hfso, selected_fields,

			 MLX5_HASH_IP_L4PORTS);

		break;



	case MLX5E_TT_IPV4_UDP:

	MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,

			 MLX5_L3_PROT_TYPE_IPV4);

		 ttconfig->l3_prot_type);

	MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,

			 MLX5_L4_PROT_TYPE_UDP);

		 ttconfig->l4_prot_type);

	MLX5_SET(rx_hash_field_select, hfso, selected_fields,

			 MLX5_HASH_IP_L4PORTS);

		break;



	case MLX5E_TT_IPV6_UDP:

		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,

			 MLX5_L3_PROT_TYPE_IPV6);

		MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,

			 MLX5_L4_PROT_TYPE_UDP);

		MLX5_SET(rx_hash_field_select, hfso, selected_fields,

			 MLX5_HASH_IP_L4PORTS);

		break;



	case MLX5E_TT_IPV4_IPSEC_AH:

		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,

			 MLX5_L3_PROT_TYPE_IPV4);

		MLX5_SET(rx_hash_field_select, hfso, selected_fields,

			 MLX5_HASH_IP_IPSEC_SPI);

		break;



	case MLX5E_TT_IPV6_IPSEC_AH:

		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,

			 MLX5_L3_PROT_TYPE_IPV6);

		MLX5_SET(rx_hash_field_select, hfso, selected_fields,

			 MLX5_HASH_IP_IPSEC_SPI);

		break;



	case MLX5E_TT_IPV4_IPSEC_ESP:

		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,

			 MLX5_L3_PROT_TYPE_IPV4);

		MLX5_SET(rx_hash_field_select, hfso, selected_fields,

			 MLX5_HASH_IP_IPSEC_SPI);

		break;



	case MLX5E_TT_IPV6_IPSEC_ESP:

		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,

			 MLX5_L3_PROT_TYPE_IPV6);

		MLX5_SET(rx_hash_field_select, hfso, selected_fields,

			 MLX5_HASH_IP_IPSEC_SPI);

		break;



	case MLX5E_TT_IPV4:

		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,

			 MLX5_L3_PROT_TYPE_IPV4);

		MLX5_SET(rx_hash_field_select, hfso, selected_fields,

			 MLX5_HASH_IP);

		break;



	case MLX5E_TT_IPV6:

		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,

			 MLX5_L3_PROT_TYPE_IPV6);

		MLX5_SET(rx_hash_field_select, hfso, selected_fields,

			 MLX5_HASH_IP);

		break;

	default:

		WARN_ONCE(true, "%s: bad traffic type!\n", __func__);

	}

		 ttconfig->rx_hash_fields);

}



void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
@@ -2746,8 +2706,9 @@ void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen) 


	for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {

		memset(tirc, 0, ctxlen);

		mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc,

					       false);

		mlx5e_build_indir_tir_ctx_hash(&priv->channels.params,

					       &tirc_default_config[tt],

					       tirc, false);

		mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);

	}
@@ -2756,8 +2717,9 @@ void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen) 


	for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {

		memset(tirc, 0, ctxlen);

		mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc,

					       true);

		mlx5e_build_indir_tir_ctx_hash(&priv->channels.params,

					       &tirc_default_config[tt],

					       tirc, true);

		mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,

				     inlen);

	}
@@ -2816,7 +2778,8 @@ static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv, 
	MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);

	MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);



	mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);

	mlx5e_build_indir_tir_ctx_hash(&priv->channels.params,

				       &tirc_default_config[tt], tirc, true);

}



static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
@@ -3208,7 +3171,9 @@ static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, 


	MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);

	MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);

	mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);



	mlx5e_build_indir_tir_ctx_hash(&priv->channels.params,

				       &tirc_default_config[tt], tirc, false);

}



static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)

drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

+3 −2
Original line number Diff line number Diff line
@@ -360,14 +360,15 @@ static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp) 
	void *tirc;



	for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {

		struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);



		memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));

		tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);



		MLX5_SET(tirc, tirc, transport_domain, hp->tdn);

		MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);

		MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);

		mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);



		mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, &ttconfig, tirc, false);

		err = mlx5_core_create_tir(hp->func_mdev, in,

					   MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);

		if (err) {