Merge "PM / devfreq: icc: Add suspend/resume APIs" (d92a6815) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/devfreq/Kconfig

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Original line number	Diff line number	Diff line
		@@ -74,6 +74,25 @@ config DEVFREQ_GOV_PASSIVE
		through sysfs entries. The passive governor recommends that
		devfreq device uses the OPP table to get the frequency/voltage.

		config QCOM_BIMC_BWMON
		tristate "QCOM BIMC Bandwidth monitor hardware"
		depends on ARCH_QCOM
		help
		The BIMC Bandwidth monitor hardware allows for monitoring the
		traffic coming from each master port connected to the BIMC. It also
		has the capability to raise an IRQ when the count exceeds a
		programmable limit.

		config DEVFREQ_GOV_QCOM_BW_HWMON
		tristate "HW monitor based governor for device BW"
		depends on QCOM_BIMC_BWMON
		help
		HW monitor based governor for device to DDR bandwidth voting.
		This governor sets the CPU BW vote by using BIMC counters to monitor
		the CPU's use of DDR. Since this uses target specific counters it
		can conflict with existing profiling tools. This governor is unlikely
		to be useful for non-QCOM devices.

		config DEVFREQ_GOV_QCOM_CACHE_HWMON
		tristate "HW monitor based governor for cache frequency"
		help
		@@ -145,6 +164,20 @@ config DEVFREQ_SIMPLE_DEV
		Device driver for simple devices that control their frequency using
		clock APIs and don't have any form of status reporting.

		config QCOM_DEVFREQ_ICC
		bool "Qualcomm Technologies Inc. DEVFREQ device for device master <-> slave IB/AB BW voting"
		depends on ARCH_QCOM
		select DEVFREQ_GOV_PERFORMANCE
		select DEVFREQ_GOV_POWERSAVE
		select DEVFREQ_GOV_USERSPACE
		select INTERCONNECT
		default n
		help
		Different devfreq governors use this devfreq device to make CPU to
		DDR IB/AB bandwidth votes. This driver provides a SoC topology
		agnostic interface to so that some of the devfreq governors can be
		shared across SoCs.

		source "drivers/devfreq/event/Kconfig"

		endif # PM_DEVFREQ

drivers/devfreq/Makefile

+3 −0

Original line number	Diff line number	Diff line
		@@ -6,6 +6,8 @@ obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE) += governor_performance.o
		obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o
		obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o
		obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
		obj-$(CONFIG_QCOM_BIMC_BWMON) += bimc-bwmon.o
		obj-$(CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON) += governor_bw_hwmon.o
		obj-$(CONFIG_DEVFREQ_GOV_QCOM_CACHE_HWMON) += governor_cache_hwmon.o

		# DEVFREQ Drivers
		@@ -13,6 +15,7 @@ obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
		obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
		obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
		obj-$(CONFIG_ARM_TEGRA20_DEVFREQ) += tegra20-devfreq.o
		obj-$(CONFIG_QCOM_DEVFREQ_ICC) += devfreq_icc.o
		obj-$(CONFIG_DEVFREQ_SIMPLE_DEV) += devfreq_simple_dev.o

		# DEVFREQ Event Drivers

drivers/devfreq/bimc-bwmon.c

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Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2014-2015, 2019, The Linux Foundation. All rights reserved.
		*/

		#define pr_fmt(fmt) "bimc-bwmon: " fmt

		#include <linux/kernel.h>
		#include <linux/module.h>
		#include <linux/init.h>
		#include <linux/io.h>
		#include <linux/delay.h>
		#include <linux/err.h>
		#include <linux/errno.h>
		#include <linux/interrupt.h>
		#include <linux/platform_device.h>
		#include <linux/of.h>
		#include <linux/spinlock.h>
		#include "governor_bw_hwmon.h"

		#define GLB_INT_STATUS(m) ((m)->global_base + 0x100)
		#define GLB_INT_CLR(m) ((m)->global_base + 0x108)
		#define GLB_INT_EN(m) ((m)->global_base + 0x10C)
		#define MON_INT_STATUS(m) ((m)->base + 0x100)
		#define MON_INT_CLR(m) ((m)->base + 0x108)
		#define MON_INT_EN(m) ((m)->base + 0x10C)
		#define MON_EN(m) ((m)->base + 0x280)
		#define MON_CLEAR(m) ((m)->base + 0x284)
		#define MON_CNT(m) ((m)->base + 0x288)
		#define MON_THRES(m) ((m)->base + 0x290)
		#define MON_MASK(m) ((m)->base + 0x298)
		#define MON_MATCH(m) ((m)->base + 0x29C)

		struct bwmon {
		void __iomem *base;
		void __iomem *global_base;
		unsigned int mport;
		unsigned int irq;
		struct device *dev;
		struct bw_hwmon hw;
		};

		#define to_bwmon(ptr) container_of(ptr, struct bwmon, hw)

		static DEFINE_SPINLOCK(glb_lock);
		static void mon_enable(struct bwmon *m)
		{
		writel_relaxed(0x1, MON_EN(m));
		}

		static void mon_disable(struct bwmon *m)
		{
		writel_relaxed(0x0, MON_EN(m));
		}

		static void mon_clear(struct bwmon *m)
		{
		writel_relaxed(0x1, MON_CLEAR(m));
		/*
		* The counter clear and IRQ clear bits are not in the same 4KB
		* region. So, we need to make sure the counter clear is completed
		* before we try to clear the IRQ or do any other counter operations.
		*/
		mb();
		}

		static void mon_irq_enable(struct bwmon *m)
		{
		u32 val;

		spin_lock(&glb_lock);
		val = readl_relaxed(GLB_INT_EN(m));
		val \|= 1 << m->mport;
		writel_relaxed(val, GLB_INT_EN(m));
		spin_unlock(&glb_lock);

		val = readl_relaxed(MON_INT_EN(m));
		val \|= 0x1;
		writel_relaxed(val, MON_INT_EN(m));
		}

		static void mon_irq_disable(struct bwmon *m)
		{
		u32 val;

		spin_lock(&glb_lock);
		val = readl_relaxed(GLB_INT_EN(m));
		val &= ~(1 << m->mport);
		writel_relaxed(val, GLB_INT_EN(m));
		spin_unlock(&glb_lock);

		val = readl_relaxed(MON_INT_EN(m));
		val &= ~0x1;
		writel_relaxed(val, MON_INT_EN(m));
		}

		static int mon_irq_status(struct bwmon *m)
		{
		u32 mval;

		mval = readl_relaxed(MON_INT_STATUS(m));

		dev_dbg(m->dev, "IRQ status p:%x, g:%x\n", mval,
		readl_relaxed(GLB_INT_STATUS(m)));

		return mval & 0x1;
		}

		static void mon_irq_clear(struct bwmon *m)
		{
		writel_relaxed(0x1, MON_INT_CLR(m));
		/* Ensure the monitor IRQ is clear before clearing GLB IRQ */
		mb();
		writel_relaxed(1 << m->mport, GLB_INT_CLR(m));
		/* Ensure the GLB IRQ clear is complete */
		mb();
		}

		static void mon_set_limit(struct bwmon *m, u32 count)
		{
		writel_relaxed(count, MON_THRES(m));
		dev_dbg(m->dev, "Thres: %08x\n", count);
		}

		static u32 mon_get_limit(struct bwmon *m)
		{
		return readl_relaxed(MON_THRES(m));
		}

		static unsigned long mon_get_count(struct bwmon *m)
		{
		unsigned long count;

		count = readl_relaxed(MON_CNT(m));
		dev_dbg(m->dev, "Counter: %08lx\n", count);
		if (mon_irq_status(m))
		count += mon_get_limit(m);
		dev_dbg(m->dev, "Actual Count: %08lx\n", count);

		return count;
		}

		/* ******** CPUBW specific code ******** */

		/* Returns MBps of read/writes for the sampling window. */
		static unsigned int bytes_to_mbps(long long bytes, unsigned int us)
		{
		bytes *= USEC_PER_SEC;
		do_div(bytes, us);
		bytes = DIV_ROUND_UP_ULL(bytes, SZ_1M);
		return bytes;
		}

		static unsigned int mbps_to_bytes(unsigned long mbps, unsigned int ms,
		unsigned int tolerance_percent)
		{
		mbps = (100 + tolerance_percent) ms;
		mbps /= 100;
		mbps = DIV_ROUND_UP(mbps, MSEC_PER_SEC);
		mbps *= SZ_1M;
		return mbps;
		}

		static unsigned long meas_bw_and_set_irq(struct bw_hwmon *hw,
		unsigned int tol, unsigned int us)
		{
		unsigned long mbps;
		u32 limit;
		unsigned int sample_ms = hw->df->profile->polling_ms;
		struct bwmon *m = to_bwmon(hw);

		mon_disable(m);

		mbps = mon_get_count(m);
		mbps = bytes_to_mbps(mbps, us);
		/*
		* The fudging of mbps when calculating limit is to workaround a HW
		* design issue. Needs further tuning.
		*/
		limit = mbps_to_bytes(max(mbps, 400UL), sample_ms, tol);
		mon_set_limit(m, limit);

		mon_clear(m);
		mon_irq_clear(m);
		mon_enable(m);

		dev_dbg(m->dev, "MBps = %lu\n", mbps);
		return mbps;
		}

		static irqreturn_t bwmon_intr_handler(int irq, void *dev)
		{
		struct bwmon *m = dev;

		if (mon_irq_status(m)) {
		update_bw_hwmon(&m->hw);
		return IRQ_HANDLED;
		}

		return IRQ_NONE;
		}

		static int start_bw_hwmon(struct bw_hwmon *hw, unsigned long mbps)
		{
		struct bwmon *m = to_bwmon(hw);
		u32 limit;
		int ret;

		ret = request_threaded_irq(m->irq, NULL, bwmon_intr_handler,
		IRQF_ONESHOT \| IRQF_SHARED,
		dev_name(m->dev), m);
		if (ret < 0) {
		dev_err(m->dev, "Unable to register interrupt handler! (%d)\n",
		ret);
		return ret;
		}

		mon_disable(m);

		limit = mbps_to_bytes(mbps, hw->df->profile->polling_ms, 0);
		mon_set_limit(m, limit);

		mon_clear(m);
		mon_irq_clear(m);
		mon_irq_enable(m);
		mon_enable(m);

		return 0;
		}

		static void stop_bw_hwmon(struct bw_hwmon *hw)
		{
		struct bwmon *m = to_bwmon(hw);

		free_irq(m->irq, m);
		mon_disable(m);
		mon_irq_disable(m);
		mon_clear(m);
		mon_irq_clear(m);
		}

		static int suspend_bw_hwmon(struct bw_hwmon *hw)
		{
		struct bwmon *m = to_bwmon(hw);

		free_irq(m->irq, m);
		mon_disable(m);
		mon_irq_disable(m);
		mon_irq_clear(m);

		return 0;
		}

		static int resume_bw_hwmon(struct bw_hwmon *hw)
		{
		struct bwmon *m = to_bwmon(hw);
		int ret;

		mon_clear(m);
		mon_irq_enable(m);
		mon_enable(m);
		ret = request_threaded_irq(m->irq, NULL, bwmon_intr_handler,
		IRQF_ONESHOT \| IRQF_SHARED,
		dev_name(m->dev), m);
		if (ret < 0) {
		dev_err(m->dev, "Unable to register interrupt handler! (%d)\n",
		ret);
		return ret;
		}

		return 0;
		}

		/*************************************************************************/

		static int bimc_bwmon_driver_probe(struct platform_device *pdev)
		{
		struct device *dev = &pdev->dev;
		struct resource *res;
		struct bwmon *m;
		int ret;
		u32 data;

		m = devm_kzalloc(dev, sizeof(*m), GFP_KERNEL);
		if (!m)
		return -ENOMEM;
		m->dev = dev;

		ret = of_property_read_u32(dev->of_node, "qcom,mport", &data);
		if (ret < 0) {
		dev_err(dev, "mport not found! (%d)\n", ret);
		return ret;
		}
		m->mport = data;

		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
		if (!res) {
		dev_err(dev, "base not found!\n");
		return -EINVAL;
		}
		m->base = devm_ioremap(dev, res->start, resource_size(res));
		if (!m->base) {
		dev_err(dev, "Unable map base!\n");
		return -ENOMEM;
		}

		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "global_base");
		if (!res) {
		dev_err(dev, "global_base not found!\n");
		return -EINVAL;
		}
		m->global_base = devm_ioremap(dev, res->start, resource_size(res));
		if (!m->global_base) {
		dev_err(dev, "Unable map global_base!\n");
		return -ENOMEM;
		}

		m->irq = platform_get_irq(pdev, 0);
		if (m->irq < 0) {
		dev_err(dev, "Unable to get IRQ number\n");
		return m->irq;
		}

		m->hw.of_node = of_parse_phandle(dev->of_node, "qcom,target-dev", 0);
		if (!m->hw.of_node)
		return -EINVAL;
		m->hw.start_hwmon = &start_bw_hwmon;
		m->hw.stop_hwmon = &stop_bw_hwmon;
		m->hw.suspend_hwmon = &suspend_bw_hwmon;
		m->hw.resume_hwmon = &resume_bw_hwmon;
		m->hw.meas_bw_and_set_irq = &meas_bw_and_set_irq;

		ret = register_bw_hwmon(dev, &m->hw);
		if (ret < 0) {
		dev_err(dev, "Dev BW hwmon registration failed: %d\n", ret);
		return ret;
		}

		return 0;
		}

		static const struct of_device_id bimc_bwmon_match_table[] = {
		{ .compatible = "qcom,bimc-bwmon" },
		{}
		};

		static struct platform_driver bimc_bwmon_driver = {
		.probe = bimc_bwmon_driver_probe,
		.driver = {
		.name = "bimc-bwmon",
		.of_match_table = bimc_bwmon_match_table,
		},
		};

		module_platform_driver(bimc_bwmon_driver);
		MODULE_DESCRIPTION("BIMC bandwidth monitor driver");
		MODULE_LICENSE("GPL v2");

drivers/devfreq/devfreq_icc.c

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		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2013-2014, 2019, The Linux Foundation. All rights reserved.
		*/

		#define pr_fmt(fmt) "devfreq-icc: " fmt

		#include <linux/kernel.h>
		#include <linux/module.h>
		#include <linux/init.h>
		#include <linux/io.h>
		#include <linux/delay.h>
		#include <linux/ktime.h>
		#include <linux/time.h>
		#include <linux/err.h>
		#include <linux/errno.h>
		#include <linux/mutex.h>
		#include <linux/interrupt.h>
		#include <linux/devfreq.h>
		#include <linux/of.h>
		#include <trace/events/power.h>
		#include <linux/platform_device.h>
		#include <linux/interconnect.h>
		#include <soc/qcom/devfreq_icc.h>

		/* Has to be ULL to prevent overflow where this macro is used. */
		#define MBYTE (1ULL << 20)

		struct dev_data {
		struct icc_path *icc_path;
		u32 cur_ab;
		u32 cur_ib;
		unsigned long gov_ab;
		struct devfreq *df;
		struct devfreq_dev_profile dp;
		};

		static int set_bw(struct device *dev, u32 new_ib, u32 new_ab)
		{
		struct dev_data *d = dev_get_drvdata(dev);
		int ret;

		if (d->cur_ib == new_ib && d->cur_ab == new_ab)
		return 0;

		dev_dbg(dev, "BW MBps: AB: %d IB: %d\n", new_ab, new_ib);

		ret = icc_set_bw(d->icc_path, Bps_to_icc(new_ab * MBYTE),
		Bps_to_icc(new_ib * MBYTE));
		if (ret < 0) {
		dev_err(dev, "icc set bandwidth request failed (%d)\n", ret);
		} else {
		d->cur_ib = new_ib;
		d->cur_ab = new_ab;
		}

		return ret;
		}

		static void find_freq(struct devfreq_dev_profile p, unsigned long freq,
		u32 flags)
		{
		int i;
		unsigned long atmost, atleast, f;

		atmost = p->freq_table[0];
		atleast = p->freq_table[p->max_state-1];
		for (i = 0; i < p->max_state; i++) {
		f = p->freq_table[i];
		if (f <= *freq)
		atmost = max(f, atmost);
		if (f >= *freq)
		atleast = min(f, atleast);
		}

		if (flags & DEVFREQ_FLAG_LEAST_UPPER_BOUND)
		*freq = atmost;
		else
		*freq = atleast;
		}

		static int icc_target(struct device dev, unsigned long freq, u32 flags)
		{
		struct dev_data *d = dev_get_drvdata(dev);

		find_freq(&d->dp, freq, flags);
		return set_bw(dev, *freq, d->gov_ab);
		}

		static int icc_get_dev_status(struct device *dev,
		struct devfreq_dev_status *stat)
		{
		struct dev_data *d = dev_get_drvdata(dev);

		stat->private_data = &d->gov_ab;
		return 0;
		}

		#define PROP_TBL "qcom,bw-tbl"
		#define PROP_ACTIVE "qcom,active-only"
		#define ACTIVE_ONLY_TAG 0x3

		int devfreq_add_icc(struct device *dev)
		{
		struct dev_data *d;
		struct devfreq_dev_profile *p;
		u32 *data;
		const char *gov_name;
		int ret, len, i;

		d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
		if (!d)
		return -ENOMEM;
		dev_set_drvdata(dev, d);

		p = &d->dp;
		p->polling_ms = 50;
		p->target = icc_target;
		p->get_dev_status = icc_get_dev_status;

		if (of_find_property(dev->of_node, PROP_TBL, &len)) {
		len /= sizeof(*data);
		data = devm_kzalloc(dev, len * sizeof(*data), GFP_KERNEL);
		if (!data)
		return -ENOMEM;

		p->freq_table = devm_kzalloc(dev,
		len * sizeof(*p->freq_table),
		GFP_KERNEL);
		if (!p->freq_table)
		return -ENOMEM;

		ret = of_property_read_u32_array(dev->of_node, PROP_TBL,
		data, len);
		if (ret < 0)
		return ret;

		for (i = 0; i < len; i++)
		p->freq_table[i] = data[i];
		p->max_state = len;
		}

		d->icc_path = of_icc_get(dev, NULL);
		if (IS_ERR(d->icc_path)) {
		ret = PTR_ERR(d->icc_path);
		if (ret != -EPROBE_DEFER)
		dev_err(dev, "Unable to register icc path: %d\n", ret);
		return ret;
		}

		if (of_property_read_bool(dev->of_node, PROP_ACTIVE))
		icc_set_tag(d->icc_path, ACTIVE_ONLY_TAG);

		if (of_property_read_string(dev->of_node, "governor", &gov_name))
		gov_name = "performance";

		d->df = devfreq_add_device(dev, p, gov_name, NULL);
		if (IS_ERR(d->df)) {
		icc_put(d->icc_path);
		return PTR_ERR(d->df);
		}

		return 0;
		}

		int devfreq_remove_icc(struct device *dev)
		{
		struct dev_data *d = dev_get_drvdata(dev);

		icc_put(d->icc_path);
		devfreq_remove_device(d->df);
		return 0;
		}

		int devfreq_suspend_icc(struct device *dev)
		{
		struct dev_data *d = dev_get_drvdata(dev);

		return devfreq_suspend_device(d->df);
		}

		int devfreq_resume_icc(struct device *dev)
		{
		struct dev_data *d = dev_get_drvdata(dev);

		return devfreq_resume_device(d->df);
		}

		static int devfreq_icc_probe(struct platform_device *pdev)
		{
		return devfreq_add_icc(&pdev->dev);
		}

		static int devfreq_icc_remove(struct platform_device *pdev)
		{
		return devfreq_remove_icc(&pdev->dev);
		}

		static const struct of_device_id devfreq_icc_match_table[] = {
		{ .compatible = "qcom,devfreq-icc" },
		{}
		};

		static struct platform_driver devfreq_icc_driver = {
		.probe = devfreq_icc_probe,
		.remove = devfreq_icc_remove,
		.driver = {
		.name = "devfreq-icc",
		.of_match_table = devfreq_icc_match_table,
		},
		};

		module_platform_driver(devfreq_icc_driver);
		MODULE_DESCRIPTION("Device DDR bandwidth voting driver MSM SoCs");
		MODULE_LICENSE("GPL v2");

drivers/devfreq/governor_bw_hwmon.c

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+556 −0

File added.

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