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Commit d8e8fd0e authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Miquel Raynal
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mtd: rawnand: denali: decouple controller and NAND chips 



Currently, this driver sticks to the legacy NAND model because it was
upstreamed before commit 2d472aba ("mtd: nand: document the NAND
controller/NAND chip DT representation"). However, relying on the
dummy_controller is already deprecated.

Switch over to the new controller/chip representation.

The struct denali_nand_info has been split into denali_controller
and denali_chip, to contain the controller data, per-chip data,
respectively.

One problem is, this commit changes the DT binding. So, as always,
the backward compatibility must be taken into consideration.

In the new binding, the controller node expects

  #address-cells = <1>;
  #size-cells = <0>;

... since the child nodes represent NAND chips.

In the old binding, the controller node may have subnodes, but they
are MTD partitions.

The denali_dt_is_legacy_binding() exploits it to distinguish old/new
platforms.

Going forward, the old binding is only allowed for existing DT files.
I updated the binding document.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
parent 13defd47

Documentation/devicetree/bindings/mtd/denali-nand.txt

+27 −13
Original line number Diff line number Diff line
@@ -7,13 +7,23 @@ Required properties: 
      "socionext,uniphier-denali-nand-v5b"  - for Socionext UniPhier (v5b)

  - reg : should contain registers location and length for data and reg.

  - reg-names: Should contain the reg names "nand_data" and "denali_reg"

  - #address-cells: should be 1. The cell encodes the chip select connection.

  - #size-cells : should be 0.

  - interrupts : The interrupt number.

  - clocks: should contain phandle of the controller core clock, the bus

    interface clock, and the ECC circuit clock.

  - clock-names: should contain "nand", "nand_x", "ecc"



Sub-nodes:

  Sub-nodes represent available NAND chips.



  Required properties:

    - reg: should contain the bank ID of the controller to which each chip

      select is connected.



  Optional properties:

  - nand-ecc-step-size: see nand.txt for details.  If present, the value must be

    - nand-ecc-step-size: see nand.txt for details.

      If present, the value must be

        512        for "altr,socfpga-denali-nand"

        1024       for "socionext,uniphier-denali-nand-v5a"

        1024       for "socionext,uniphier-denali-nand-v5b"
@@ -23,18 +33,22 @@ Optional properties: 
        8, 16      for "socionext,uniphier-denali-nand-v5b"

    - nand-ecc-maximize: see nand.txt for details



The device tree may optionally contain sub-nodes describing partitions of the

The chip nodes may optionally contain sub-nodes describing partitions of the

address space. See partition.txt for more detail.



Examples:



nand: nand@ff900000 {

	#address-cells = <1>;

	#size-cells = <1>;

	#size-cells = <0>;

	compatible = "altr,socfpga-denali-nand";

	reg = <0xff900000 0x20>, <0xffb80000 0x1000>;

	reg-names = "nand_data", "denali_reg";

	clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;

	clock-names = "nand", "nand_x", "ecc";

	interrupts = <0 144 4>;



	nand@0 {

		reg = <0>;

	}

};