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Commit d8df260a authored by Chinh T Cao's avatar Chinh T Cao Committed by Jeff Kirsher
Browse files

ice : Ensure only valid bits are set in ice_aq_set_phy_cfg 



In the ice_aq_set_phy_cfg AQ command, the 16.4 bit is reserved. This
patch will make sure that this bit will never be set to 1.

Signed-off-by: default avatarChinh T Cao <chinh.t.cao@intel.com>
Reviewed-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Signed-off-by: default avatarAnirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 16c3301b

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

+3 −2
Original line number Original line Diff line number Diff line
@@ -953,6 +953,7 @@ struct ice_aqc_set_phy_cfg_data { 
	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */

	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */

	__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */

	__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */

	u8 caps;

	u8 caps;

#define ICE_AQ_PHY_ENA_VALID_MASK	ICE_M(0xef, 0)

#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY	BIT(0)

#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY	BIT(0)

#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY	BIT(1)

#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY	BIT(1)

#define ICE_AQ_PHY_ENA_LOW_POWER	BIT(2)

#define ICE_AQ_PHY_ENA_LOW_POWER	BIT(2)

drivers/net/ethernet/intel/ice/ice_common.c

+11 −0
Original line number Original line Diff line number Diff line
@@ -1929,6 +1929,15 @@ ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport, 
	if (!cfg)

	if (!cfg)

		return ICE_ERR_PARAM;

		return ICE_ERR_PARAM;





	/* Ensure that only valid bits of cfg->caps can be turned on. */

	if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {

		ice_debug(hw, ICE_DBG_PHY,

			  "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",

			  cfg->caps);



		cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;

	}



	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);

	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);

	desc.params.set_phy.lport_num = lport;

	desc.params.set_phy.lport_num = lport;

	desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);

	desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
@@ -2027,8 +2036,10 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 
	/* clear the old pause settings */

	/* clear the old pause settings */

	cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |

	cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |

				   ICE_AQC_PHY_EN_RX_LINK_PAUSE);

				   ICE_AQC_PHY_EN_RX_LINK_PAUSE);



	/* set the new capabilities */

	/* set the new capabilities */

	cfg.caps |= pause_mask;

	cfg.caps |= pause_mask;



	/* If the capabilities have changed, then set the new config */

	/* If the capabilities have changed, then set the new config */

	if (cfg.caps != pcaps->caps) {

	if (cfg.caps != pcaps->caps) {

		int retry_count, retry_max = 10;

		int retry_count, retry_max = 10;

drivers/net/ethernet/intel/ice/ice_type.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -24,6 +24,7 @@ static inline bool ice_is_tc_ena(u8 bitmap, u8 tc) 
/* debug masks - set these bits in hw->debug_mask to control output */

/* debug masks - set these bits in hw->debug_mask to control output */

#define ICE_DBG_INIT		BIT_ULL(1)

#define ICE_DBG_INIT		BIT_ULL(1)

#define ICE_DBG_LINK		BIT_ULL(4)

#define ICE_DBG_LINK		BIT_ULL(4)

#define ICE_DBG_PHY		BIT_ULL(5)

#define ICE_DBG_QCTX		BIT_ULL(6)

#define ICE_DBG_QCTX		BIT_ULL(6)

#define ICE_DBG_NVM		BIT_ULL(7)

#define ICE_DBG_NVM		BIT_ULL(7)

#define ICE_DBG_LAN		BIT_ULL(8)

#define ICE_DBG_LAN		BIT_ULL(8)