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Commit d8d1c351 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'x86/mm' into x86/asm to resolve conflict and to create common base 



 Conflicts:
	arch/x86/include/asm/cpufeature.h

Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents cb44d0cf 1886297c

Documentation/x86/pat.txt

+32 −0
Original line number Original line Diff line number Diff line
@@ -196,3 +196,35 @@ Another, more verbose way of getting PAT related debug messages is with 
"debugpat" boot parameter. With this parameter, various debug messages are

"debugpat" boot parameter. With this parameter, various debug messages are

printed to dmesg log.

printed to dmesg log.





PAT Initialization

------------------



The following table describes how PAT is initialized under various

configurations. The PAT MSR must be updated by Linux in order to support WC

and WT attributes. Otherwise, the PAT MSR has the value programmed in it

by the firmware. Note, Xen enables WC attribute in the PAT MSR for guests.



 MTRR PAT   Call Sequence               PAT State  PAT MSR

 =========================================================

 E    E     MTRR -> PAT init            Enabled    OS

 E    D     MTRR -> PAT init            Disabled    -

 D    E     MTRR -> PAT disable         Disabled   BIOS

 D    D     MTRR -> PAT disable         Disabled    -

 -    np/E  PAT  -> PAT disable         Disabled   BIOS

 -    np/D  PAT  -> PAT disable         Disabled    -

 E    !P/E  MTRR -> PAT init            Disabled   BIOS

 D    !P/E  MTRR -> PAT disable         Disabled   BIOS

 !M   !P/E  MTRR stub -> PAT disable    Disabled   BIOS



 Legend

 ------------------------------------------------

 E         Feature enabled in CPU

 D	   Feature disabled/unsupported in CPU

 np	   "nopat" boot option specified

 !P	   CONFIG_X86_PAT option unset

 !M	   CONFIG_MTRR option unset

 Enabled   PAT state set to enabled

 Disabled  PAT state set to disabled

 OS        PAT initializes PAT MSR with OS setting

 BIOS      PAT keeps PAT MSR with BIOS setting

arch/x86/include/asm/cpufeature.h

+0 −1
Original line number Original line Diff line number Diff line
@@ -126,7 +126,6 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; 
#define cpu_has_aes		boot_cpu_has(X86_FEATURE_AES)

#define cpu_has_aes		boot_cpu_has(X86_FEATURE_AES)

#define cpu_has_avx		boot_cpu_has(X86_FEATURE_AVX)

#define cpu_has_avx		boot_cpu_has(X86_FEATURE_AVX)

#define cpu_has_avx2		boot_cpu_has(X86_FEATURE_AVX2)

#define cpu_has_avx2		boot_cpu_has(X86_FEATURE_AVX2)

#define cpu_has_pat		boot_cpu_has(X86_FEATURE_PAT)

#define cpu_has_xsave		boot_cpu_has(X86_FEATURE_XSAVE)

#define cpu_has_xsave		boot_cpu_has(X86_FEATURE_XSAVE)

#define cpu_has_xsaves		boot_cpu_has(X86_FEATURE_XSAVES)

#define cpu_has_xsaves		boot_cpu_has(X86_FEATURE_XSAVES)

/*

/*

arch/x86/include/asm/mtrr.h

+5 −1
Original line number Original line Diff line number Diff line
@@ -24,6 +24,7 @@ 
#define _ASM_X86_MTRR_H

#define _ASM_X86_MTRR_H





#include <uapi/asm/mtrr.h>

#include <uapi/asm/mtrr.h>

#include <asm/pat.h>









/*

/*
@@ -83,9 +84,12 @@ static inline int mtrr_trim_uncached_memory(unsigned long end_pfn) 
static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)

static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)

{

{

}

}

static inline void mtrr_bp_init(void)

{

	pat_disable("MTRRs disabled, skipping PAT initialization too.");

}





#define mtrr_ap_init() do {} while (0)

#define mtrr_ap_init() do {} while (0)

#define mtrr_bp_init() do {} while (0)

#define set_mtrr_aps_delayed_init() do {} while (0)

#define set_mtrr_aps_delayed_init() do {} while (0)

#define mtrr_aps_init() do {} while (0)

#define mtrr_aps_init() do {} while (0)

#define mtrr_bp_restore() do {} while (0)

#define mtrr_bp_restore() do {} while (0)

arch/x86/include/asm/pat.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -5,8 +5,8 @@ 
#include <asm/pgtable_types.h>

#include <asm/pgtable_types.h>





bool pat_enabled(void);

bool pat_enabled(void);

void pat_disable(const char *reason);

extern void pat_init(void);

extern void pat_init(void);

void pat_init_cache_modes(u64);





extern int reserve_memtype(u64 start, u64 end,

extern int reserve_memtype(u64 start, u64 end,

		enum page_cache_mode req_pcm, enum page_cache_mode *ret_pcm);

		enum page_cache_mode req_pcm, enum page_cache_mode *ret_pcm);

arch/x86/kernel/cpu/mtrr/generic.c

+14 −10
Original line number Original line Diff line number Diff line
@@ -444,11 +444,24 @@ static void __init print_mtrr_state(void) 
		pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);

		pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);

}

}





/* PAT setup for BP. We need to go through sync steps here */

void __init mtrr_bp_pat_init(void)

{

	unsigned long flags;



	local_irq_save(flags);

	prepare_set();



	pat_init();



	post_set();

	local_irq_restore(flags);

}



/* Grab all of the MTRR state for this CPU into *state */

/* Grab all of the MTRR state for this CPU into *state */

bool __init get_mtrr_state(void)

bool __init get_mtrr_state(void)

{

{

	struct mtrr_var_range *vrs;

	struct mtrr_var_range *vrs;

	unsigned long flags;

	unsigned lo, dummy;

	unsigned lo, dummy;

	unsigned int i;

	unsigned int i;
@@ -481,15 +494,6 @@ bool __init get_mtrr_state(void) 




	mtrr_state_set = 1;

	mtrr_state_set = 1;





	/* PAT setup for BP. We need to go through sync steps here */

	local_irq_save(flags);

	prepare_set();



	pat_init();



	post_set();

	local_irq_restore(flags);



	return !!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED);

	return !!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED);

}

}