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Commit d8cf9372 authored by Vinod Koul's avatar Vinod Koul Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8150: Add apps shared nodes 



Add hwlock, pmu, smem, tcsr_mutex_regs, apss_shared mailbox, apps_rsc
including the rpmhcc child nodes to the SM8150 DTSI

Co-developed-by: default avatarSibi Sankar <sibis@codeaurora.org>
Signed-off-by: default avatarSibi Sankar <sibis@codeaurora.org>
Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
Reviewed-by: default avatarNiklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: default avatarAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 912c373a

arch/arm64/boot/dts/qcom/sm8150.dtsi

+63 −0
Original line number Diff line number Diff line
@@ -144,12 +144,23 @@ 
		};

	};



	tcsr_mutex: hwlock {

		compatible = "qcom,tcsr-mutex";

		syscon = <&tcsr_mutex_regs 0 0x1000>;

		#hwlock-cells = <1>;

	};



	memory@80000000 {

		device_type = "memory";

		/* We expect the bootloader to fill in the size */

		reg = <0x0 0x80000000 0x0 0x0>;

	};



	pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";
@@ -266,6 +277,12 @@ 
		};

	};



	smem {

		compatible = "qcom,smem";

		memory-region = <&smem_mem>;

		hwlocks = <&tcsr_mutex 3>;

	};



	soc: soc@0 {

		#address-cells = <2>;

		#size-cells = <2>;
@@ -306,6 +323,11 @@ 
			};

		};



		tcsr_mutex_regs: syscon@1f40000 {

			compatible = "syscon";

			reg = <0x0 0x01f40000 0x0 0x40000>;

		};



		tlmm: pinctrl@3100000 {

			compatible = "qcom,sm8150-pinctrl";

			reg = <0x0 0x03100000 0x0 0x300000>,
@@ -321,6 +343,16 @@ 
			#interrupt-cells = <2>;

		};



		aoss_qmp: power-controller@c300000 {

			compatible = "qcom,sm8150-aoss-qmp";

			reg = <0x0 0x0c300000 0x0 0x100000>;

			interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;

			mboxes = <&apss_shared 0>;



			#clock-cells = <0>;

			#power-domain-cells = <1>;

		};



		spmi_bus: spmi@c440000 {

			compatible = "qcom,spmi-pmic-arb";

			reg = <0x0 0x0c440000 0x0 0x0001100>,
@@ -349,6 +381,12 @@ 
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		};



		apss_shared: mailbox@17c00000 {

			compatible = "qcom,sm8150-apss-shared";

			reg = <0x0 0x17c00000 0x0 0x1000>;

			#mbox-cells = <1>;

		};



		timer@17c20000 {

			#address-cells = <2>;

			#size-cells = <2>;
@@ -407,6 +445,31 @@ 
				status = "disabled";

			};

		};



		apps_rsc: rsc@18200000 {

			label = "apps_rsc";

			compatible = "qcom,rpmh-rsc";

			reg = <0x0 0x18200000 0x0 0x10000>,

			      <0x0 0x18210000 0x0 0x10000>,

			      <0x0 0x18220000 0x0 0x10000>;

			reg-names = "drv-0", "drv-1", "drv-2";

			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;

			qcom,tcs-offset = <0xd00>;

			qcom,drv-id = <2>;

			qcom,tcs-config = <ACTIVE_TCS  2>,

					  <SLEEP_TCS   1>,

					  <WAKE_TCS    1>,

					  <CONTROL_TCS 0>;



			rpmhcc: clock-controller {

				compatible = "qcom,sm8150-rpmh-clk";

				#clock-cells = <1>;

				clock-names = "xo";

				clocks = <&xo_board>;

			};

		};

	};



	timer {