Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d86c8eaf authored by Andi Kleen's avatar Andi Kleen Committed by Ingo Molnar
Browse files

perf/x86/intel: Document all Haswell models



Add names for each Haswell model as requested by Peter.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1409683455-29168-2-git-send-email-andi@firstfloor.org


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent b7614685
Loading
Loading
Loading
Loading
+4 −4
Original line number Original line Diff line number Diff line
@@ -2540,10 +2540,10 @@ __init int intel_pmu_init(void)
		break;
		break;




	case 60: /* 22nm Haswell */
	case 60: /* 22nm Haswell Core */
	case 63:
	case 63: /* 22nm Haswell Server */
	case 69:
	case 69: /* 22nm Haswell ULT */
	case 70:
	case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
		x86_pmu.late_ack = true;
		x86_pmu.late_ack = true;
		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
		memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
		memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));