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Commit d82fd29c authored Oct 09, 2018 by Christophe Leroy Committed by Michael Ellerman Oct 14, 2018

powerpc/mm: Distribute platform specific PAGE and PMD flags and definitions



The base kernel PAGE_XXXX definition sets are more or less platform
specific. Lets distribute them close to platform _PAGE_XXX flags
definition, and customise them to their exact platform flags.

Also defines _PAGE_PSIZE and _PTE_NONE_MASK for each platform
allthough they are defined as 0.

Do the same with _PMD flags like _PMD_USER and _PMD_PRESENT_MASK

Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

parent e0f57031

arch/powerpc/include/asm/nohash/32/pte-40x.h

+29 −0

Original line number	Original line	Diff line number	Diff line
	@@ -50,13 +50,42 @@
	#define _PAGE_EXEC 0x200 /* hardware: EX permission */		#define _PAGE_EXEC 0x200 /* hardware: EX permission */
	#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */		#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */

			/* No page size encoding in the linux PTE */
			#define _PAGE_PSIZE 0

			#define _PAGE_KERNEL_RO 0
			#define _PAGE_KERNEL_ROX _PAGE_EXEC
			#define _PAGE_KERNEL_RW (_PAGE_DIRTY \| _PAGE_RW \| _PAGE_HWWRITE)
			#define _PAGE_KERNEL_RWX (_PAGE_DIRTY \| _PAGE_RW \| _PAGE_HWWRITE \| _PAGE_EXEC)

	#define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */		#define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
			#define _PMD_PRESENT_MASK _PMD_PRESENT
	#define _PMD_BAD 0x802		#define _PMD_BAD 0x802
	#define _PMD_SIZE_4M 0x0c0		#define _PMD_SIZE_4M 0x0c0
	#define _PMD_SIZE_16M 0x0e0		#define _PMD_SIZE_16M 0x0e0
			#define _PMD_USER 0

			#define _PTE_NONE_MASK 0

	/* Until my rework is finished, 40x still needs atomic PTE updates */		/* Until my rework is finished, 40x still needs atomic PTE updates */
	#define PTE_ATOMIC_UPDATES 1		#define PTE_ATOMIC_UPDATES 1

			/* Mask of bits returned by pte_pgprot() */
			#define PAGE_PROT_BITS (_PAGE_GUARDED \| _PAGE_NO_CACHE \| \
			_PAGE_WRITETHRU \| _PAGE_USER \| _PAGE_ACCESSED \| \
			_PAGE_RW \| _PAGE_HWWRITE \| _PAGE_DIRTY \| _PAGE_EXEC)

			#define _PAGE_BASE_NC (_PAGE_PRESENT \| _PAGE_ACCESSED)
			#define _PAGE_BASE (_PAGE_BASE_NC)

			/* Permission masks used to generate the __P and __S table */
			#define PAGE_NONE __pgprot(_PAGE_BASE)
			#define PAGE_SHARED __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_RW)
			#define PAGE_SHARED_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_RW \| _PAGE_EXEC)
			#define PAGE_COPY __pgprot(_PAGE_BASE \| _PAGE_USER)
			#define PAGE_COPY_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_EXEC)
			#define PAGE_READONLY __pgprot(_PAGE_BASE \| _PAGE_USER)
			#define PAGE_READONLY_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_EXEC)

	#endif /* __KERNEL__ */		#endif /* __KERNEL__ */
	#endif /* _ASM_POWERPC_NOHASH_32_PTE_40x_H */		#endif /* _ASM_POWERPC_NOHASH_32_PTE_40x_H */

arch/powerpc/include/asm/nohash/32/pte-44x.h

+35 −0

Original line number	Original line	Diff line number	Diff line
	@@ -85,14 +85,49 @@
	#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */		#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
	#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */		#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */

			/* No page size encoding in the linux PTE */
			#define _PAGE_PSIZE 0

			#define _PAGE_KERNEL_RO 0
			#define _PAGE_KERNEL_ROX _PAGE_EXEC
			#define _PAGE_KERNEL_RW (_PAGE_DIRTY \| _PAGE_RW)
			#define _PAGE_KERNEL_RWX (_PAGE_DIRTY \| _PAGE_RW \| _PAGE_EXEC)

			/* Mask of bits returned by pte_pgprot() */
			#define PAGE_PROT_BITS (_PAGE_GUARDED \| _PAGE_COHERENT \| _PAGE_NO_CACHE \| \
			_PAGE_WRITETHRU \| _PAGE_USER \| _PAGE_ACCESSED \| \
			_PAGE_RW \| _PAGE_DIRTY \| _PAGE_EXEC)

	/* TODO: Add large page lowmem mapping support */		/* TODO: Add large page lowmem mapping support */
	#define _PMD_PRESENT 0		#define _PMD_PRESENT 0
	#define _PMD_PRESENT_MASK (PAGE_MASK)		#define _PMD_PRESENT_MASK (PAGE_MASK)
	#define _PMD_BAD (~PAGE_MASK)		#define _PMD_BAD (~PAGE_MASK)
			#define _PMD_USER 0

	/* ERPN in a PTE never gets cleared, ignore it */		/* ERPN in a PTE never gets cleared, ignore it */
	#define _PTE_NONE_MASK 0xffffffff00000000ULL		#define _PTE_NONE_MASK 0xffffffff00000000ULL

			/*
			* We define 2 sets of base prot bits, one for basic pages (ie,
			* cacheable kernel and user pages) and one for non cacheable
			* pages. We always set _PAGE_COHERENT when SMP is enabled or
			* the processor might need it for DMA coherency.
			*/
			#define _PAGE_BASE_NC (_PAGE_PRESENT \| _PAGE_ACCESSED)
			#if defined(CONFIG_SMP)
			#define _PAGE_BASE (_PAGE_BASE_NC \| _PAGE_COHERENT)
			#else
			#define _PAGE_BASE (_PAGE_BASE_NC)
			#endif

			/* Permission masks used to generate the __P and __S table */
			#define PAGE_NONE __pgprot(_PAGE_BASE)
			#define PAGE_SHARED __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_RW)
			#define PAGE_SHARED_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_RW \| _PAGE_EXEC)
			#define PAGE_COPY __pgprot(_PAGE_BASE \| _PAGE_USER)
			#define PAGE_COPY_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_EXEC)
			#define PAGE_READONLY __pgprot(_PAGE_BASE \| _PAGE_USER)
			#define PAGE_READONLY_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_EXEC)

	#endif /* __KERNEL__ */		#endif /* __KERNEL__ */
	#endif /* _ASM_POWERPC_NOHASH_32_PTE_44x_H */		#endif /* _ASM_POWERPC_NOHASH_32_PTE_44x_H */

arch/powerpc/include/asm/nohash/32/pte-8xx.h

+27 −0

Original line number	Original line	Diff line number	Diff line
	@@ -46,19 +46,46 @@
	#define _PAGE_NA 0x0200 /* Supervisor NA, User no access */		#define _PAGE_NA 0x0200 /* Supervisor NA, User no access */
	#define _PAGE_RO 0x0600 /* Supervisor RO, User no access */		#define _PAGE_RO 0x0600 /* Supervisor RO, User no access */

			#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED \| _PAGE_RO)
			#define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED \| _PAGE_RO \| _PAGE_EXEC)
			#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED \| _PAGE_DIRTY)
			#define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED \| _PAGE_DIRTY \| _PAGE_EXEC)

			/* Mask of bits returned by pte_pgprot() */
			#define PAGE_PROT_BITS (_PAGE_GUARDED \| _PAGE_NO_CACHE \| \
			_PAGE_ACCESSED \| _PAGE_RO \| _PAGE_NA \| \
			_PAGE_PRIVILEGED \| _PAGE_DIRTY \| _PAGE_EXEC)

	#define _PMD_PRESENT 0x0001		#define _PMD_PRESENT 0x0001
			#define _PMD_PRESENT_MASK _PMD_PRESENT
	#define _PMD_BAD 0x0fd0		#define _PMD_BAD 0x0fd0
	#define _PMD_PAGE_MASK 0x000c		#define _PMD_PAGE_MASK 0x000c
	#define _PMD_PAGE_8M 0x000c		#define _PMD_PAGE_8M 0x000c
	#define _PMD_PAGE_512K 0x0004		#define _PMD_PAGE_512K 0x0004
	#define _PMD_USER 0x0020 /* APG 1 */		#define _PMD_USER 0x0020 /* APG 1 */

			#define _PTE_NONE_MASK 0

	/* Until my rework is finished, 8xx still needs atomic PTE updates */		/* Until my rework is finished, 8xx still needs atomic PTE updates */
	#define PTE_ATOMIC_UPDATES 1		#define PTE_ATOMIC_UPDATES 1

	#ifdef CONFIG_PPC_16K_PAGES		#ifdef CONFIG_PPC_16K_PAGES
	#define _PAGE_PSIZE _PAGE_HUGE		#define _PAGE_PSIZE _PAGE_HUGE
			#else
			#define _PAGE_PSIZE 0
	#endif		#endif

			#define _PAGE_BASE_NC (_PAGE_PRESENT \| _PAGE_ACCESSED \| _PAGE_PSIZE)
			#define _PAGE_BASE (_PAGE_BASE_NC)

			/* Permission masks used to generate the __P and __S table */
			#define PAGE_NONE __pgprot(_PAGE_BASE \| _PAGE_NA)
			#define PAGE_SHARED __pgprot(_PAGE_BASE)
			#define PAGE_SHARED_X __pgprot(_PAGE_BASE \| _PAGE_EXEC)
			#define PAGE_COPY __pgprot(_PAGE_BASE \| _PAGE_RO)
			#define PAGE_COPY_X __pgprot(_PAGE_BASE \| _PAGE_RO \| _PAGE_EXEC)
			#define PAGE_READONLY __pgprot(_PAGE_BASE \| _PAGE_RO)
			#define PAGE_READONLY_X __pgprot(_PAGE_BASE \| _PAGE_RO \| _PAGE_EXEC)

	#endif /* __KERNEL__ */		#endif /* __KERNEL__ */
	#endif /* _ASM_POWERPC_NOHASH_32_PTE_8xx_H */		#endif /* _ASM_POWERPC_NOHASH_32_PTE_8xx_H */

arch/powerpc/include/asm/nohash/32/pte-fsl-booke.h

+38 −0

Original line number	Original line	Diff line number	Diff line
	@@ -31,11 +31,49 @@
	#define _PAGE_WRITETHRU 0x00400 /* H: W bit */		#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
	#define _PAGE_SPECIAL 0x00800 /* S: Special page */		#define _PAGE_SPECIAL 0x00800 /* S: Special page */

			#define _PAGE_KERNEL_RO 0
			#define _PAGE_KERNEL_ROX _PAGE_EXEC
			#define _PAGE_KERNEL_RW (_PAGE_DIRTY \| _PAGE_RW)
			#define _PAGE_KERNEL_RWX (_PAGE_DIRTY \| _PAGE_RW \| _PAGE_EXEC)

			/* No page size encoding in the linux PTE */
			#define _PAGE_PSIZE 0

			/* Mask of bits returned by pte_pgprot() */
			#define PAGE_PROT_BITS (_PAGE_GUARDED \| _PAGE_COHERENT \| _PAGE_NO_CACHE \| \
			_PAGE_WRITETHRU \| _PAGE_USER \| _PAGE_ACCESSED \| \
			_PAGE_RW \| _PAGE_DIRTY \| _PAGE_EXEC)

	#define _PMD_PRESENT 0		#define _PMD_PRESENT 0
	#define _PMD_PRESENT_MASK (PAGE_MASK)		#define _PMD_PRESENT_MASK (PAGE_MASK)
	#define _PMD_BAD (~PAGE_MASK)		#define _PMD_BAD (~PAGE_MASK)
			#define _PMD_USER 0

			#define _PTE_NONE_MASK 0

	#define PTE_WIMGE_SHIFT (6)		#define PTE_WIMGE_SHIFT (6)

			/*
			* We define 2 sets of base prot bits, one for basic pages (ie,
			* cacheable kernel and user pages) and one for non cacheable
			* pages. We always set _PAGE_COHERENT when SMP is enabled or
			* the processor might need it for DMA coherency.
			*/
			#define _PAGE_BASE_NC (_PAGE_PRESENT \| _PAGE_ACCESSED)
			#if defined(CONFIG_SMP) \|\| defined(CONFIG_PPC_E500MC)
			#define _PAGE_BASE (_PAGE_BASE_NC \| _PAGE_COHERENT)
			#else
			#define _PAGE_BASE (_PAGE_BASE_NC)
			#endif

			/* Permission masks used to generate the __P and __S table */
			#define PAGE_NONE __pgprot(_PAGE_BASE)
			#define PAGE_SHARED __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_RW)
			#define PAGE_SHARED_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_RW \| _PAGE_EXEC)
			#define PAGE_COPY __pgprot(_PAGE_BASE \| _PAGE_USER)
			#define PAGE_COPY_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_EXEC)
			#define PAGE_READONLY __pgprot(_PAGE_BASE \| _PAGE_USER)
			#define PAGE_READONLY_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_EXEC)

	#endif /* __KERNEL__ */		#endif /* __KERNEL__ */
	#endif /* _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H */		#endif /* _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H */

arch/powerpc/include/asm/nohash/pte-book3e.h

+30 −0

Original line number	Original line	Diff line number	Diff line
	@@ -77,7 +77,37 @@
	#define _PMD_PRESENT 0		#define _PMD_PRESENT 0
	#define _PMD_PRESENT_MASK (PAGE_MASK)		#define _PMD_PRESENT_MASK (PAGE_MASK)
	#define _PMD_BAD (~PAGE_MASK)		#define _PMD_BAD (~PAGE_MASK)
			#define _PMD_USER 0
			#else
			#define _PTE_NONE_MASK 0
	#endif		#endif

			/* Mask of bits returned by pte_pgprot() */
			#define PAGE_PROT_BITS (_PAGE_GUARDED \| _PAGE_COHERENT \| _PAGE_NO_CACHE \| \
			_PAGE_WRITETHRU \| _PAGE_USER \| _PAGE_ACCESSED \| \
			_PAGE_PRIVILEGED \| _PAGE_RW \| _PAGE_DIRTY \| _PAGE_EXEC)

			/*
			* We define 2 sets of base prot bits, one for basic pages (ie,
			* cacheable kernel and user pages) and one for non cacheable
			* pages. We always set _PAGE_COHERENT when SMP is enabled or
			* the processor might need it for DMA coherency.
			*/
			#define _PAGE_BASE_NC (_PAGE_PRESENT \| _PAGE_ACCESSED \| _PAGE_PSIZE)
			#if defined(CONFIG_SMP)
			#define _PAGE_BASE (_PAGE_BASE_NC \| _PAGE_COHERENT)
			#else
			#define _PAGE_BASE (_PAGE_BASE_NC)
			#endif

			/* Permission masks used to generate the __P and __S table */
			#define PAGE_NONE __pgprot(_PAGE_BASE)
			#define PAGE_SHARED __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_RW)
			#define PAGE_SHARED_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_RW \| _PAGE_EXEC)
			#define PAGE_COPY __pgprot(_PAGE_BASE \| _PAGE_USER)
			#define PAGE_COPY_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_EXEC)
			#define PAGE_READONLY __pgprot(_PAGE_BASE \| _PAGE_USER)
			#define PAGE_READONLY_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_EXEC)

	#endif /* __KERNEL__ */		#endif /* __KERNEL__ */
	#endif /* _ASM_POWERPC_NOHASH_PTE_BOOK3E_H */		#endif /* _ASM_POWERPC_NOHASH_PTE_BOOK3E_H */