Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d7d8fb70 authored by Neil Armstrong's avatar Neil Armstrong Committed by Andrzej Hajda
Browse files

drm/meson: add HDMI div40 TMDS mode 



Add support for TMDS Clock > 3.4GHz for HDMI2.0 display modes.

Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1549022873-40549-3-git-send-email-narmstrong@baylibre.com
parent 264fce6c

drivers/gpu/drm/meson/meson_dw_hdmi.c

+19 −4
Original line number Diff line number Diff line
@@ -365,7 +365,8 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 
	unsigned int wr_clk =

		readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING));



	DRM_DEBUG_DRIVER("\"%s\"\n", mode->name);

	DRM_DEBUG_DRIVER("\"%s\" div%d\n", mode->name,

			 mode->clock > 340000 ? 40 : 10);



	/* Enable clocks */

	regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
@@ -385,9 +386,17 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 
	/* Enable normal output to PHY */

	dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));



	/* TMDS pattern setup (TOFIX pattern for 4k2k scrambling) */

	dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f);

	dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f);

	/* TMDS pattern setup (TOFIX Handle the YUV420 case) */

	if (mode->clock > 340000) {

		dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0);

		dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,

				  0x03ff03ff);

	} else {

		dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,

				  0x001f001f);

		dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,

				  0x001f001f);

	}



	/* Load TMDS pattern */

	dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1);
@@ -413,6 +422,8 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 
	/* Disable clock, fifo, fifo_wr */

	regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0);



	dw_hdmi_set_high_tmds_clock_ratio(hdmi);



	msleep(100);



	/* Reset PHY 3 times in a row */
@@ -557,6 +568,10 @@ dw_hdmi_mode_valid(struct drm_connector *connector, 


	DRM_DEBUG_DRIVER("Modeline " DRM_MODE_FMT "\n", DRM_MODE_ARG(mode));



	/* If sink max TMDS clock, we reject the mode */

	if (mode->clock > connector->display_info.max_tmds_clock)

		return MODE_BAD;



	/* Check against non-VIC supported modes */

	if (!vic) {

		status = meson_venc_hdmi_supported_mode(mode);