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Commit d77ab5d3 authored by Tony Truong's avatar Tony Truong
Browse files

msm: pcie: remove deprecated explicit clock retention support 



Configurable clock retention is no longer supported. Remove all
support from PCIe root complex driver.

Change-Id: I5a028e42e7bbdf00c6c0867368b5cb6f6555595e
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent cfab905a

drivers/pci/controller/pci-msm.c

+45 −79
Original line number Diff line number Diff line
@@ -4,7 +4,6 @@ 
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>

#include <linux/bitops.h>

#include <linux/clk.h>

#include <linux/clk/qcom.h>

#include <linux/compiler.h>

#include <linux/crc8.h>

#include <linux/debugfs.h>
@@ -515,7 +514,6 @@ struct msm_pcie_clk_info_t { 
	struct clk *hdl;

	char *name;

	u32 freq;

	bool config_mem;

	bool required;

	/*

	 * Suppressible clocks are not turned off during drv suspend.
@@ -848,52 +846,52 @@ msm_pcie_pipe_reset_info[MAX_RC_NUM][MSM_PCIE_MAX_PIPE_RESET] = { 
static struct msm_pcie_clk_info_t

	msm_pcie_clk_info[MAX_RC_NUM][MSM_PCIE_MAX_CLK] = {

	{

	{NULL, "pcie_0_ref_clk_src", 0, false, false, false},

	{NULL, "pcie_0_aux_clk", 1010000, false, true, false},

	{NULL, "pcie_0_cfg_ahb_clk", 0, false, true, false},

	{NULL, "pcie_0_mstr_axi_clk", 0, true, true, false},

	{NULL, "pcie_0_slv_axi_clk", 0, true, true, false},

	{NULL, "pcie_0_ldo", 0, false, true, true},

	{NULL, "pcie_0_smmu_clk", 0, false, false, false},

	{NULL, "pcie_0_slv_q2a_axi_clk", 0, false, false, false},

	{NULL, "pcie_0_sleep_clk", 0, false, false, false},

	{NULL, "pcie_phy_refgen_clk", 0, false, false, true},

	{NULL, "pcie_tbu_clk", 0, false, false, true},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false, true},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false, false},

	{NULL, "pcie_phy_aux_clk", 0, false, false, false}

	{NULL, "pcie_0_ref_clk_src", 0, false, false},

	{NULL, "pcie_0_aux_clk", 1010000, true, false},

	{NULL, "pcie_0_cfg_ahb_clk", 0, true, false},

	{NULL, "pcie_0_mstr_axi_clk", 0, true, false},

	{NULL, "pcie_0_slv_axi_clk", 0, true, false},

	{NULL, "pcie_0_ldo", 0, true, true},

	{NULL, "pcie_0_smmu_clk", 0, false, false},

	{NULL, "pcie_0_slv_q2a_axi_clk", 0, false, false},

	{NULL, "pcie_0_sleep_clk", 0, false, false},

	{NULL, "pcie_phy_refgen_clk", 0, false, true},

	{NULL, "pcie_tbu_clk", 0, false, true},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},

	{NULL, "pcie_phy_aux_clk", 0, false, false}

	},

	{

	{NULL, "pcie_1_ref_clk_src", 0, false, false, false},

	{NULL, "pcie_1_aux_clk", 1010000, false, true, false},

	{NULL, "pcie_1_cfg_ahb_clk", 0, false, true, false},

	{NULL, "pcie_1_mstr_axi_clk", 0, true, true, false},

	{NULL, "pcie_1_slv_axi_clk", 0, true, true, false},

	{NULL, "pcie_1_ldo", 0, false, true, true},

	{NULL, "pcie_1_smmu_clk", 0, false, false, false},

	{NULL, "pcie_1_slv_q2a_axi_clk", 0, false, false, false},

	{NULL, "pcie_1_sleep_clk", 0, false, false, false},

	{NULL, "pcie_phy_refgen_clk", 0, false, false, true},

	{NULL, "pcie_tbu_clk", 0, false, false, true},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false, true},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false, false},

	{NULL, "pcie_phy_aux_clk", 0, false, false, false}

	{NULL, "pcie_1_ref_clk_src", 0, false, false},

	{NULL, "pcie_1_aux_clk", 1010000, true, false},

	{NULL, "pcie_1_cfg_ahb_clk", 0, true, false},

	{NULL, "pcie_1_mstr_axi_clk", 0, true, false},

	{NULL, "pcie_1_slv_axi_clk", 0, true, false},

	{NULL, "pcie_1_ldo", 0, true, true},

	{NULL, "pcie_1_smmu_clk", 0, false, false},

	{NULL, "pcie_1_slv_q2a_axi_clk", 0, false, false},

	{NULL, "pcie_1_sleep_clk", 0, false, false},

	{NULL, "pcie_phy_refgen_clk", 0, false, true},

	{NULL, "pcie_tbu_clk", 0, false, true},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},

	{NULL, "pcie_phy_aux_clk", 0, false, false}

	},

	{

	{NULL, "pcie_2_ref_clk_src", 0, false, false, false},

	{NULL, "pcie_2_aux_clk", 1010000, false, true, false},

	{NULL, "pcie_2_cfg_ahb_clk", 0, false, true, false},

	{NULL, "pcie_2_mstr_axi_clk", 0, true, true, false},

	{NULL, "pcie_2_slv_axi_clk", 0, true, true, false},

	{NULL, "pcie_2_ldo", 0, false, true, true},

	{NULL, "pcie_2_smmu_clk", 0, false, false, false},

	{NULL, "pcie_2_slv_q2a_axi_clk", 0, false, false, false},

	{NULL, "pcie_2_sleep_clk", 0, false, false, false},

	{NULL, "pcie_phy_refgen_clk", 0, false, false, true},

	{NULL, "pcie_tbu_clk", 0, false, false, true},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false, true},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false, false},

	{NULL, "pcie_phy_aux_clk", 0, false, false, false}

	{NULL, "pcie_2_ref_clk_src", 0, false, false},

	{NULL, "pcie_2_aux_clk", 1010000, true, false},

	{NULL, "pcie_2_cfg_ahb_clk", 0, true, false},

	{NULL, "pcie_2_mstr_axi_clk", 0, true, false},

	{NULL, "pcie_2_slv_axi_clk", 0, true, false},

	{NULL, "pcie_2_ldo", 0, true, true},

	{NULL, "pcie_2_smmu_clk", 0, false, false},

	{NULL, "pcie_2_slv_q2a_axi_clk", 0, false, false},

	{NULL, "pcie_2_sleep_clk", 0, false, false},

	{NULL, "pcie_phy_refgen_clk", 0, false, true},

	{NULL, "pcie_tbu_clk", 0, false, true},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},

	{NULL, "pcie_phy_aux_clk", 0, false, false}

	}

};
@@ -901,13 +899,13 @@ static struct msm_pcie_clk_info_t 
static struct msm_pcie_clk_info_t

	msm_pcie_pipe_clk_info[MAX_RC_NUM][MSM_PCIE_MAX_PIPE_CLK] = {

	{

	{NULL, "pcie_0_pipe_clk", 125000000, true, true, false},

	{NULL, "pcie_0_pipe_clk", 125000000, true, false},

	},

	{

	{NULL, "pcie_1_pipe_clk", 125000000, true, true, false},

	{NULL, "pcie_1_pipe_clk", 125000000, true, false},

	},

	{

	{NULL, "pcie_2_pipe_clk", 125000000, true, true, false},

	{NULL, "pcie_2_pipe_clk", 125000000, true, false},

	}

};
@@ -989,32 +987,6 @@ static void msm_pcie_config_clear_set_dword(struct pci_dev *pdev, 
	pci_write_config_dword(pdev, pos, val);

}



static inline void msm_pcie_config_clock_mem(struct msm_pcie_dev_t *dev,

	struct msm_pcie_clk_info_t *info)

{

	int ret;



	ret = clk_set_flags(info->hdl, CLKFLAG_NORETAIN_MEM);

	if (ret)

		PCIE_ERR(dev,

			"PCIe: RC%d can't configure core memory for clk %s: %d.\n",

			dev->rc_idx, info->name, ret);

	else

		PCIE_DBG2(dev,

			"PCIe: RC%d configured core memory for clk %s.\n",

			dev->rc_idx, info->name);



	ret = clk_set_flags(info->hdl, CLKFLAG_NORETAIN_PERIPH);

	if (ret)

		PCIE_ERR(dev,

			"PCIe: RC%d can't configure peripheral memory for clk %s: %d.\n",

			dev->rc_idx, info->name, ret);

	else

		PCIE_DBG2(dev,

			"PCIe: RC%d configured peripheral memory for clk %s.\n",

			dev->rc_idx, info->name);

}



static void msm_pcie_rumi_init(struct msm_pcie_dev_t *pcie_dev)

{

	u32 val;
@@ -3131,9 +3103,6 @@ static int msm_pcie_clk_init(struct msm_pcie_dev_t *dev) 
		if (!info->hdl)

			continue;



		if (info->config_mem)

			msm_pcie_config_clock_mem(dev, info);



		if (info->freq) {

			if (!strcmp(info->name, "pcie_phy_refgen_clk")) {

				mutex_lock(&dev->clk_lock);
@@ -3266,9 +3235,6 @@ static int msm_pcie_pipe_clk_init(struct msm_pcie_dev_t *dev) 
		if (!info->hdl)

			continue;



		if (info->config_mem)

			msm_pcie_config_clock_mem(dev, info);



		if (info->freq) {

			rc = clk_set_rate(info->hdl, info->freq);

			if (rc) {