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Commit d7784ea6 authored by Harshdeep Dhatt's avatar Harshdeep Dhatt
Browse files

msm: kgsl: Add target specific clock and bus scaling 



This allows us to define target specific clock and bus scaling
functions. Also, get rid of the dcvs_set function pointer
from gmu core ops.

Change-Id: I137ea0071958bfdd73a266d734e278703f0dc722
Signed-off-by: default avatarHarshdeep Dhatt <hdhatt@codeaurora.org>
parent f7954ed2

drivers/gpu/msm/adreno-gpulist.h

+6 −6
Original line number Diff line number Diff line
@@ -782,7 +782,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = { 
		.features = ADRENO_RPMH | ADRENO_IFPC |

			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION |

			ADRENO_IOCOHERENT | ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.gpudev = &adreno_a630_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.bus_width = 32,
@@ -881,7 +881,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = { 
		.features = ADRENO_RPMH | ADRENO_PREEMPTION |

			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.gpudev = &adreno_a630_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -908,7 +908,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = { 
		.features = ADRENO_RPMH | ADRENO_PREEMPTION |

			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.gpudev = &adreno_a630_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -935,7 +935,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619 = { 
		.features = ADRENO_RPMH | ADRENO_PREEMPTION |

			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.gpudev = &adreno_a630_gpudev,

		.gmem_size = SZ_512K,

		.bus_width = 32,

	},
@@ -1080,7 +1080,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = { 
			ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |

			ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |

			ADRENO_APRIV,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.gpudev = &adreno_a630_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -1407,7 +1407,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = { 
		.features = ADRENO_RPMH | ADRENO_PREEMPTION |

			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.gpudev = &adreno_a630_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,

drivers/gpu/msm/adreno.c

+52 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#include <linux/delay.h>

#include <linux/firmware.h>

#include <linux/input.h>

#include <linux/interconnect.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/of_device.h>
@@ -3799,6 +3800,55 @@ int adreno_power_cycle_u32(struct adreno_device *adreno_dev, 
	return ret;

}



static int adreno_gpu_clock_set(struct kgsl_device *device, u32 pwrlevel)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	const struct adreno_power_ops *ops = ADRENO_POWER_OPS(adreno_dev);

	struct kgsl_pwrctrl *pwr = &device->pwrctrl;

	struct kgsl_pwrlevel *pl = &pwr->pwrlevels[pwrlevel];

	int ret;



	if (ops->gpu_clock_set)

		return ops->gpu_clock_set(adreno_dev, pwrlevel);



	ret = clk_set_rate(pwr->grp_clks[0], pl->gpu_freq);

	if (ret)

		dev_err(device->dev, "GPU clk freq set failure: %d\n", ret);



	return ret;

}



static int adreno_interconnect_bus_set(struct adreno_device *adreno_dev,

	int level, u32 ab)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct kgsl_pwrctrl *pwr = &device->pwrctrl;



	if ((level == pwr->cur_buslevel) && (ab == pwr->cur_ab))

		return 0;



	pwr->cur_buslevel = level;

	pwr->cur_ab = ab;



	icc_set_bw(pwr->icc_path, MBps_to_icc(ab),

		kBps_to_icc(pwr->ddr_table[level]));



	trace_kgsl_buslevel(device, pwr->active_pwrlevel, level);



	return 0;

}



static int adreno_gpu_bus_set(struct kgsl_device *device, int level, u32 ab)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	const struct adreno_power_ops *ops = ADRENO_POWER_OPS(adreno_dev);



	if (ops->gpu_bus_set)

		return ops->gpu_bus_set(adreno_dev, level, ab);



	return adreno_interconnect_bus_set(adreno_dev, level, ab);

}



static const struct kgsl_functable adreno_functable = {

	/* Mandatory functions */

	.regread = adreno_regread,
@@ -3842,6 +3892,8 @@ static const struct kgsl_functable adreno_functable = { 
	.stop_fault_timer = adreno_dispatcher_stop_fault_timer,

	.query_property_list = adreno_query_property_list,

	.is_hwcg_on = adreno_is_hwcg_on,

	.gpu_clock_set = adreno_gpu_clock_set,

	.gpu_bus_set = adreno_gpu_bus_set,

};



static const struct component_master_ops adreno_ops = {

drivers/gpu/msm/adreno.h

+6 −0
Original line number Diff line number Diff line
@@ -361,6 +361,11 @@ struct adreno_power_ops { 
	 * @touch_wakeup: Target specific function to start gpu on touch event

	 */

	void (*touch_wakeup)(struct adreno_device *adreno_dev);

	/** @gpu_clock_set: Target specific function to set gpu frequency */

	int (*gpu_clock_set)(struct adreno_device *adreno_dev, u32 pwrlevel);

	/** @gpu_bus_set: Target specific function to set gpu bandwidth */

	int (*gpu_bus_set)(struct adreno_device *adreno_dev, int bus_level,

		u32 ab);

};



/**
@@ -911,6 +916,7 @@ extern struct adreno_gpudev adreno_a5xx_gpudev; 
extern struct adreno_gpudev adreno_a6xx_gpudev;

extern struct adreno_gpudev adreno_a6xx_gmu_gpudev;

extern struct adreno_gpudev adreno_a6xx_rgmu_gpudev;

extern struct adreno_gpudev adreno_a630_gpudev;



extern int adreno_wake_nice;

extern unsigned int adreno_wake_timeout;

drivers/gpu/msm/adreno_a6xx.c

+35 −0
Original line number Diff line number Diff line
@@ -2747,3 +2747,38 @@ struct adreno_gpudev adreno_a6xx_rgmu_gpudev = { 
	.read_alwayson = a6xx_read_alwayson,

	.power_ops = &a6xx_rgmu_power_ops,

};



struct adreno_gpudev adreno_a630_gpudev = {

	.reg_offsets = a6xx_register_offsets,

	.probe = a6xx_gmu_device_probe,

	.start = a6xx_start,

	.snapshot = a6xx_snapshot,

	.init = a6xx_init,

	.irq_handler = a6xx_irq_handler,

	.rb_start = a6xx_rb_start,

	.regulator_enable = a6xx_sptprac_enable,

	.regulator_disable = a6xx_sptprac_disable,

	.perfcounters = &a6xx_perfcounters,

	.read_throttling_counters = a6xx_read_throttling_counters,

	.microcode_read = a6xx_microcode_read,

	.gpu_keepalive = a6xx_gpu_keepalive,

	.hw_isidle = a6xx_hw_isidle,

	.iommu_fault_block = a6xx_iommu_fault_block,

	.reset = a6xx_gmu_restart,

	.preemption_pre_ibsubmit = a6xx_preemption_pre_ibsubmit,

	.preemption_post_ibsubmit = a6xx_preemption_post_ibsubmit,

	.preemption_init = a6xx_preemption_init,

	.preemption_schedule = a6xx_preemption_schedule,

	.set_marker = a6xx_set_marker,

	.preemption_context_init = a6xx_preemption_context_init,

	.preemption_context_destroy = a6xx_preemption_context_destroy,

	.sptprac_is_on = a6xx_sptprac_is_on,

	.ccu_invalidate = a6xx_ccu_invalidate,

	.perfcounter_update = a6xx_perfcounter_update,

#ifdef CONFIG_QCOM_KGSL_CORESIGHT

	.coresight = {&a6xx_coresight, &a6xx_coresight_cx},

#endif

	.clk_set_options = a6xx_clk_set_options,

	.read_alwayson = a6xx_read_alwayson,

	.power_ops = &a630_gmu_power_ops,

};

drivers/gpu/msm/adreno_a6xx.h

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 


extern const struct adreno_power_ops a6xx_gmu_power_ops;

extern const struct adreno_power_ops a6xx_rgmu_power_ops;

extern const struct adreno_power_ops a630_gmu_power_ops;



/**

 * struct a6xx_device - Container for the a6xx_device