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Commit d7337ca2 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: support retrieving and adjusting SOC clock power levels V2 



User can use "pp_dpm_socclk" to retrieve and adjust SOC clock power
levels.

V2: expose this interface for Vega10 and later ASICs only

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7ca881a8

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

+52 −2
Original line number Diff line number Diff line
@@ -680,11 +680,13 @@ static ssize_t amdgpu_get_ppfeature_status(struct device *dev, 
}



/**

 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie

 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_pcie

 *

 * The amdgpu driver provides a sysfs API for adjusting what power levels

 * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,

 * and pp_dpm_pcie are used for this.

 * pp_dpm_socclk and pp_dpm_pcie are used for this.

 *

 * pp_dpm_socclk interface is only available for Vega10 and later ASICs.

 *

 * Reading back the files will show you the available power levels within

 * the power state and the clock information for those levels.
@@ -804,6 +806,42 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, 
	return count;

}



static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,

		struct device_attribute *attr,

		char *buf)

{

	struct drm_device *ddev = dev_get_drvdata(dev);

	struct amdgpu_device *adev = ddev->dev_private;



	if (adev->powerplay.pp_funcs->print_clock_levels)

		return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);

	else

		return snprintf(buf, PAGE_SIZE, "\n");

}



static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,

		struct device_attribute *attr,

		const char *buf,

		size_t count)

{

	struct drm_device *ddev = dev_get_drvdata(dev);

	struct amdgpu_device *adev = ddev->dev_private;

	int ret;

	uint32_t mask = 0;



	ret = amdgpu_read_mask(buf, count, &mask);

	if (ret)

		return ret;



	if (adev->powerplay.pp_funcs->force_clock_level)

		ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);



	if (ret)

		return -EINVAL;



	return count;

}



static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,

		struct device_attribute *attr,

		char *buf)
@@ -1087,6 +1125,9 @@ static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR, 
static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,

		amdgpu_get_pp_dpm_mclk,

		amdgpu_set_pp_dpm_mclk);

static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,

		amdgpu_get_pp_dpm_socclk,

		amdgpu_set_pp_dpm_socclk);

static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,

		amdgpu_get_pp_dpm_pcie,

		amdgpu_set_pp_dpm_pcie);
@@ -2246,6 +2287,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) 
		DRM_ERROR("failed to create device file pp_dpm_mclk\n");

		return ret;

	}

	if (adev->asic_type >= CHIP_VEGA10) {

		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);

		if (ret) {

			DRM_ERROR("failed to create device file pp_dpm_socclk\n");

			return ret;

		}

	}

	ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);

	if (ret) {

		DRM_ERROR("failed to create device file pp_dpm_pcie\n");
@@ -2333,6 +2381,8 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) 


	device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);

	device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);

	if (adev->asic_type >= CHIP_VEGA10)

		device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);

	device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);

	device_remove_file(adev->dev, &dev_attr_pp_sclk_od);

	device_remove_file(adev->dev, &dev_attr_pp_mclk_od);

drivers/gpu/drm/amd/include/kgd_pp_interface.h

+1 −0
Original line number Diff line number Diff line
@@ -92,6 +92,7 @@ enum pp_clock_type { 
	PP_SCLK,

	PP_MCLK,

	PP_PCIE,

	PP_SOCCLK,

	OD_SCLK,

	OD_MCLK,

	OD_VDDC_CURVE,

drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

+45 −0
Original line number Diff line number Diff line
@@ -2296,6 +2296,34 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr, 


		break;



	case PP_SOCCLK:

		soft_min_level = mask ? (ffs(mask) - 1) : 0;

		soft_max_level = mask ? (fls(mask) - 1) : 0;



		if (soft_max_level >= data->dpm_table.soc_table.count) {

			pr_err("Clock level specified %d is over max allowed %d\n",

					soft_max_level,

					data->dpm_table.soc_table.count - 1);

			return -EINVAL;

		}



		data->dpm_table.soc_table.dpm_state.soft_min_level =

			data->dpm_table.soc_table.dpm_levels[soft_min_level].value;

		data->dpm_table.soc_table.dpm_state.soft_max_level =

			data->dpm_table.soc_table.dpm_levels[soft_max_level].value;



		ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);

		PP_ASSERT_WITH_CODE(!ret,

			"Failed to upload boot level to lowest!",

			return ret);



		ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);

		PP_ASSERT_WITH_CODE(!ret,

			"Failed to upload dpm max level to highest!",

			return ret);



		break;



	case PP_PCIE:

		soft_min_level = mask ? (ffs(mask) - 1) : 0;

		soft_max_level = mask ? (fls(mask) - 1) : 0;
@@ -2931,6 +2959,23 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, 
				(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");

		break;



	case PP_SOCCLK:

		ret = vega20_get_current_clk_freq(hwmgr, PPCLK_SOCCLK, &now);

		PP_ASSERT_WITH_CODE(!ret,

				"Attempt to get current socclk freq Failed!",

				return ret);



		ret = vega20_get_socclocks(hwmgr, &clocks);

		PP_ASSERT_WITH_CODE(!ret,

				"Attempt to get soc clk levels Failed!",

				return ret);



		for (i = 0; i < clocks.num_levels; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",

				i, clocks.data[i].clocks_in_khz / 1000,

				(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");

		break;



	case PP_PCIE:

		gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &

			     PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)