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Commit d70229f7 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon/kms: add dpm support for trinity asics



This adds dpm support for trinity asics.  This includes:
- clockgating
- powergating
- dynamic engine clock scaling
- dynamic voltage scaling

set radeon.dpm=1 to enable it.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 80ea2c12
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+2 −1
Original line number Diff line number Diff line
@@ -78,7 +78,8 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
	atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
	si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \
	r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \
	rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o
	rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \
	trinity_smc.o

radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
+10 −3
Original line number Diff line number Diff line
@@ -4187,6 +4187,10 @@ int evergreen_irq_set(struct radeon_device *rdev)
	hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
	hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
	hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
	if (rdev->family == CHIP_ARUBA)
		thermal_int = RREG32(TN_CG_THERMAL_INT_CTRL) &
			~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
	else
		thermal_int = RREG32(CG_THERMAL_INT) &
			~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);

@@ -4360,6 +4364,9 @@ int evergreen_irq_set(struct radeon_device *rdev)
	WREG32(DC_HPD4_INT_CONTROL, hpd4);
	WREG32(DC_HPD5_INT_CONTROL, hpd5);
	WREG32(DC_HPD6_INT_CONTROL, hpd6);
	if (rdev->family == CHIP_ARUBA)
		WREG32(TN_CG_THERMAL_INT_CTRL, thermal_int);
	else
		WREG32(CG_THERMAL_INT, thermal_int);

	WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
+10 −0
Original line number Diff line number Diff line
@@ -823,6 +823,16 @@
#define 	THERM_INT_MASK_HIGH			(1 << 24)
#define 	THERM_INT_MASK_LOW			(1 << 25)

#define	TN_CG_THERMAL_INT_CTRL				0x738
#define		TN_DIG_THERM_INTH(x)			((x) << 0)
#define		TN_DIG_THERM_INTH_MASK			0x000000FF
#define		TN_DIG_THERM_INTH_SHIFT			0
#define		TN_DIG_THERM_INTL(x)			((x) << 8)
#define		TN_DIG_THERM_INTL_MASK			0x0000FF00
#define		TN_DIG_THERM_INTL_SHIFT			8
#define 	TN_THERM_INT_MASK_HIGH			(1 << 24)
#define 	TN_THERM_INT_MASK_LOW			(1 << 25)

#define	CG_MULT_THERMAL_STATUS				0x740
#define		ASIC_T(x)			        ((x) << 16)
#define		ASIC_T_MASK			        0x07FF0000
+9 −1
Original line number Diff line number Diff line
@@ -71,7 +71,15 @@ typedef uint8_t PPSMC_Result;
#define PPSMC_MSG_ExitULV                   ((uint8_t)0x65)
#define PPSMC_MSG_ResetToDefaults           ((uint8_t)0x84)

typedef uint8_t PPSMC_Msg;
/* TN */
#define PPSMC_MSG_DPM_Config                ((uint32_t) 0x102)
#define PPSMC_MSG_DPM_ForceState            ((uint32_t) 0x104)
#define PPSMC_MSG_PG_SIMD_Config            ((uint32_t) 0x108)
#define PPSMC_MSG_DCE_RemoveVoltageAdjustment   ((uint32_t) 0x11d)
#define PPSMC_MSG_DCE_AllowVoltageAdjustment    ((uint32_t) 0x11e)


typedef uint16_t PPSMC_Msg;

#pragma pack(pop)

+12 −0
Original line number Diff line number Diff line
@@ -2064,6 +2064,18 @@ static struct radeon_asic trinity_asic = {
		.set_uvd_clocks = &sumo_set_uvd_clocks,
		.get_temperature = &tn_get_temp,
	},
	.dpm = {
		.init = &trinity_dpm_init,
		.setup_asic = &trinity_dpm_setup_asic,
		.enable = &trinity_dpm_enable,
		.disable = &trinity_dpm_disable,
		.set_power_state = &trinity_dpm_set_power_state,
		.display_configuration_changed = &trinity_dpm_display_configuration_changed,
		.fini = &trinity_dpm_fini,
		.get_sclk = &trinity_dpm_get_sclk,
		.get_mclk = &trinity_dpm_get_mclk,
		.print_power_state = &trinity_dpm_print_power_state,
	},
	.pflip = {
		.pre_page_flip = &evergreen_pre_page_flip,
		.page_flip = &evergreen_page_flip,
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