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Commit d6ef139c authored by Oleksij Rempel's avatar Oleksij Rempel Committed by Jassi Brar
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dt-bindings: mailbox: imx-mu: add generic MU channel support



Each MU has four pairs of rx/tx data register with four rx/tx interrupts
which can also be used as a separate channel.

Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarOleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: default avatarJassi Brar <jaswinder.singh@linaro.org>
parent 480285bd
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+23 −3
Original line number Diff line number Diff line
@@ -18,11 +18,31 @@ Messaging Unit Device Node:
Required properties:
-------------------
- compatible :	should be "fsl,<chip>-mu", the supported chips include
		imx8qxp, imx8qm.
		imx6sx, imx7s, imx8qxp, imx8qm.
		The "fsl,imx6sx-mu" compatible is seen as generic and should
		be included together with SoC specific compatible.
- reg :		Should contain the registers location and length
- interrupts :	Interrupt number. The interrupt specifier format depends
		on the interrupt controller parent.
- #mbox-cells:  Must be 0. Number of cells in a mailbox
- #mbox-cells:  Must be 2.
			  <&phandle type channel>
			    phandle   : Label name of controller
			    type      : Channel type
			    channel   : Channel number

		This MU support 4 type of unidirectional channels, each type
		has 4 channels. A total of 16 channels. Following types are
		supported:
		0 - TX channel with 32bit transmit register and IRQ transmit
		acknowledgment support.
		1 - RX channel with 32bit receive register and IRQ support
		2 - TX doorbell channel. Without own register and no ACK support.
		3 - RX doorbell channel.

Optional properties:
-------------------
- clocks :	phandle to the input clock.
- fsl,mu-side-b : Should be set for side B MU.

Examples:
--------
@@ -30,5 +50,5 @@ lsio_mu0: mailbox@5d1b0000 {
	compatible = "fsl,imx8qxp-mu";
	reg = <0x0 0x5d1b0000 0x0 0x10000>;
	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	#mbox-cells = <0>;
	#mbox-cells = <2>;
};