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Commit d6e0cbb1 authored by Tao Zhou's avatar Tao Zhou Committed by Alex Deucher
Browse files

drm/amdgpu: implement querying ras error count for mmhub 



get mmhub ea ras error count by accessing EDC_CNT register

Signed-off-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarGuchun Chen <guchun.chen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f0f50dcf

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+55 −0
Original line number Diff line number Diff line
@@ -21,11 +21,13 @@ 
 *

 */

#include "amdgpu.h"

#include "amdgpu_ras.h"

#include "mmhub_v1_0.h"



#include "mmhub/mmhub_1_0_offset.h"

#include "mmhub/mmhub_1_0_sh_mask.h"

#include "mmhub/mmhub_1_0_default.h"

#include "mmhub/mmhub_9_4_0_offset.h"

#include "vega10_enum.h"



#include "soc15_common.h"
@@ -33,6 +35,9 @@ 
#define mmDAGB0_CNTL_MISC2_RV 0x008f

#define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0



#define EA_EDC_CNT_MASK 0x3

#define EA_EDC_CNT_SHIFT 0x2



u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)

{

	u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
@@ -557,6 +562,56 @@ void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 
static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,

					   void *ras_error_status)

{

	int i;

	uint32_t ea0_edc_cnt, ea0_edc_cnt2;

	uint32_t ea1_edc_cnt, ea1_edc_cnt2;

	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;



	/* EDC CNT will be cleared automatically after read */

	ea0_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT_VG20);

	ea0_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20);

	ea1_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT_VG20);

	ea1_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20);



	/* error count of each error type is recorded by 2 bits,

	 * ce and ue count in EDC_CNT

	 */

	for (i = 0; i < 5; i++) {

		err_data->ce_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);

		err_data->ce_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);

		ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;

		ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;

		err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);

		err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);

		ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;

		ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;

	}

	/* successive ue count in EDC_CNT */

	for (i = 0; i < 5; i++) {

		err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);

		err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);

		ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;

		ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;

	}



	/* ce and ue count in EDC_CNT2 */

	for (i = 0; i < 3; i++) {

		err_data->ce_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);

		err_data->ce_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);

		ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;

		ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;

		err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);

		err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);

		ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;

		ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;

	}

	/* successive ue count in EDC_CNT2 */

	for (i = 0; i < 6; i++) {

		err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);

		err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);

		ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;

		ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;

	}

}



const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h

+21 −0
Original line number Diff line number Diff line
@@ -21,6 +21,27 @@ 
#ifndef _mmhub_9_4_0_OFFSET_HEADER

#define _mmhub_9_4_0_OFFSET_HEADER



/* MMEA */

#define mmMMEA0_SDP_ARB_FINAL_VG20                                                                     0x01ee

#define mmMMEA0_SDP_ARB_FINAL_VG20_BASE_IDX                                                            0

#define mmMMEA0_EDC_CNT_VG20                                                                           0x0206

#define mmMMEA0_EDC_CNT_VG20_BASE_IDX                                                                  0

#define mmMMEA0_EDC_CNT2_VG20                                                                          0x0207

#define mmMMEA0_EDC_CNT2_VG20_BASE_IDX                                                                 0

#define mmMMEA0_EDC_MODE_VG20                                                                          0x0210

#define mmMMEA0_EDC_MODE_VG20_BASE_IDX                                                                 0

#define mmMMEA0_ERR_STATUS_VG20                                                                        0x0211

#define mmMMEA0_ERR_STATUS_VG20_BASE_IDX                                                               0

#define mmMMEA1_SDP_ARB_FINAL_VG20                                                                     0x032e

#define mmMMEA1_SDP_ARB_FINAL_VG20_BASE_IDX                                                            0

#define mmMMEA1_EDC_CNT_VG20                                                                           0x0346

#define mmMMEA1_EDC_CNT_VG20_BASE_IDX                                                                  0

#define mmMMEA1_EDC_CNT2_VG20                                                                          0x0347

#define mmMMEA1_EDC_CNT2_VG20_BASE_IDX                                                                 0

#define mmMMEA1_EDC_MODE_VG20                                                                          0x0350

#define mmMMEA1_EDC_MODE_VG20_BASE_IDX                                                                 0

#define mmMMEA1_ERR_STATUS_VG20                                                                        0x0351

#define mmMMEA1_ERR_STATUS_VG20_BASE_IDX                                                               0



// addressBlock: mmhub_utcl2_vmsharedpfdec

// base address: 0x6a040

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h

+222 −0

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