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Commit d6d99a3f authored by Yuval Mintz's avatar Yuval Mintz Committed by David S. Miller
Browse files

bnx2x: revised and corrected SPIO access 



Changed naming convention of SPIO macros, and prevented access to invalid SPIOs.

Signed-off-by: default avatarYuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d317966b

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

+20 −23
Original line number Original line Diff line number Diff line
@@ -2032,40 +2032,39 @@ int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 
	return 0;

	return 0;

}

}





static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)

static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)

{

{

	u32 spio_mask = (1 << spio_num);

	u32 spio_reg;

	u32 spio_reg;





	if ((spio_num < MISC_REGISTERS_SPIO_4) ||

	/* Only 2 SPIOs are configurable */

	    (spio_num > MISC_REGISTERS_SPIO_7)) {

	if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {

		BNX2X_ERR("Invalid SPIO %d\n", spio_num);

		BNX2X_ERR("Invalid SPIO 0x%x\n", spio);

		return -EINVAL;

		return -EINVAL;

	}

	}





	bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);

	bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);

	/* read SPIO and mask except the float bits */

	/* read SPIO and mask except the float bits */

	spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);

	spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);





	switch (mode) {

	switch (mode) {

	case MISC_REGISTERS_SPIO_OUTPUT_LOW:

	case MISC_SPIO_OUTPUT_LOW:

		DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num);

		DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);

		/* clear FLOAT and set CLR */

		/* clear FLOAT and set CLR */

		spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);

		spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);

		spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);

		spio_reg |=  (spio << MISC_SPIO_CLR_POS);

		break;

		break;





	case MISC_REGISTERS_SPIO_OUTPUT_HIGH:

	case MISC_SPIO_OUTPUT_HIGH:

		DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num);

		DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);

		/* clear FLOAT and set SET */

		/* clear FLOAT and set SET */

		spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);

		spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);

		spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_SET_POS);

		spio_reg |=  (spio << MISC_SPIO_SET_POS);

		break;

		break;





	case MISC_REGISTERS_SPIO_INPUT_HI_Z:

	case MISC_SPIO_INPUT_HI_Z:

		DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num);

		DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);

		/* set FLOAT */

		/* set FLOAT */

		spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);

		spio_reg |= (spio << MISC_SPIO_FLOAT_POS);

		break;

		break;





	default:

	default:
@@ -6196,18 +6195,16 @@ static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 
		return;

		return;





	/* Fan failure is indicated by SPIO 5 */

	/* Fan failure is indicated by SPIO 5 */

	bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,

	bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);

		       MISC_REGISTERS_SPIO_INPUT_HI_Z);





	/* set to active low mode */

	/* set to active low mode */

	val = REG_RD(bp, MISC_REG_SPIO_INT);

	val = REG_RD(bp, MISC_REG_SPIO_INT);

	val |= ((1 << MISC_REGISTERS_SPIO_5) <<

	val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);

					MISC_REGISTERS_SPIO_INT_OLD_SET_POS);

	REG_WR(bp, MISC_REG_SPIO_INT, val);

	REG_WR(bp, MISC_REG_SPIO_INT, val);





	/* enable interrupt to signal the IGU */

	/* enable interrupt to signal the IGU */

	val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);

	val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);

	val |= (1 << MISC_REGISTERS_SPIO_5);

	val |= MISC_SPIO_SPIO5;

	REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);

	REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);

}

}
@@ -6969,7 +6966,7 @@ static int bnx2x_init_hw_port(struct bnx2x *bp) 




	/* If SPIO5 is set to generate interrupts, enable it for this port */

	/* If SPIO5 is set to generate interrupts, enable it for this port */

	val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);

	val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);

	if (val & (1 << MISC_REGISTERS_SPIO_5)) {

	if (val & MISC_SPIO_SPIO5) {

		u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :

		u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :

				       MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);

				       MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);

		val = REG_RD(bp, reg_addr);

		val = REG_RD(bp, reg_addr);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h

+10 −0
Original line number Original line Diff line number Diff line
@@ -5942,6 +5942,16 @@ 
#define MISC_REGISTERS_SPIO_OUTPUT_HIGH 			 1

#define MISC_REGISTERS_SPIO_OUTPUT_HIGH 			 1

#define MISC_REGISTERS_SPIO_OUTPUT_LOW				 0

#define MISC_REGISTERS_SPIO_OUTPUT_LOW				 0

#define MISC_REGISTERS_SPIO_SET_POS				 8

#define MISC_REGISTERS_SPIO_SET_POS				 8

#define MISC_SPIO_CLR_POS					 16

#define MISC_SPIO_FLOAT					 (0xffL<<24)

#define MISC_SPIO_FLOAT_POS					 24

#define MISC_SPIO_INPUT_HI_Z					 2

#define MISC_SPIO_INT_OLD_SET_POS				 16

#define MISC_SPIO_OUTPUT_HIGH					 1

#define MISC_SPIO_OUTPUT_LOW					 0

#define MISC_SPIO_SET_POS					 8

#define MISC_SPIO_SPIO4					 0x10

#define MISC_SPIO_SPIO5					 0x20

#define HW_LOCK_MAX_RESOURCE_VALUE				 31

#define HW_LOCK_MAX_RESOURCE_VALUE				 31

#define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB				 13

#define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB				 13

#define HW_LOCK_RESOURCE_DRV_FLAGS				 10

#define HW_LOCK_RESOURCE_DRV_FLAGS				 10