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Commit d6504846 authored by Jayachandran C's avatar Jayachandran C Committed by John Crispin
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MIPS: Netlogic: select MIPSR2 for XLP 



This allows us to use the r2 optimized code from kernel headers
while compilation.

Disable PGD_C0_CONTEXT option for XLP, which does not work.

Signed-off-by: default avatarJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4456


Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
parent 4be3d2f3

arch/mips/Kconfig

+2 −1
Original line number Original line Diff line number Diff line
@@ -1542,6 +1542,7 @@ config CPU_XLP 
	select WEAK_ORDERING

	select WEAK_ORDERING

	select WEAK_REORDERING_BEYOND_LLSC

	select WEAK_REORDERING_BEYOND_LLSC

	select CPU_HAS_PREFETCH

	select CPU_HAS_PREFETCH

	select CPU_MIPSR2

	help

	help

	  Netlogic Microsystems XLP processors.

	  Netlogic Microsystems XLP processors.

endchoice

endchoice
@@ -1755,7 +1756,7 @@ config CPU_SUPPORTS_UNCACHED_ACCELERATED 
	bool

	bool

config MIPS_PGD_C0_CONTEXT

config MIPS_PGD_C0_CONTEXT

	bool

	bool

	default y if 64BIT && CPU_MIPSR2

	default y if 64BIT && CPU_MIPSR2 && !CPU_XLP





#

#

# Set to y for ptrace access to watch registers.

# Set to y for ptrace access to watch registers.