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Commit d64a45c0 authored by Christophe Leroy's avatar Christophe Leroy Committed by Greg Kroah-Hartman
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spi: fsl-spi: Re-organise transfer bits_per_word adaptation 



(backported from upstream 8a5299a1278eadf1e08a598a5345c376206f171e)

For different reasons, fsl-spi driver performs bits_per_word
modifications for different reasons:
- On CPU mode, to minimise amount of interrupts
- On CPM/QE mode to work around controller byte order

For CPU mode that's done in fsl_spi_prepare_message() while
for CPM mode that's done in fsl_spi_setup_transfer().

Reunify all of it in fsl_spi_prepare_message(), and catch
impossible cases early through master's bits_per_word_mask
instead of returning EINVAL later.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/0ce96fe96e8b07cba0613e4097cfd94d09b8919a.1680371809.git.christophe.leroy@csgroup.eu


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent aabe8ca7

drivers/spi/spi-fsl-spi.c

+23 −27
Original line number Diff line number Diff line
@@ -204,26 +204,6 @@ static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, 
	return bits_per_word;

}



static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,

				struct spi_device *spi,

				int bits_per_word)

{

	/* CPM/QE uses Little Endian for words > 8

	 * so transform 16 and 32 bits words into 8 bits

	 * Unfortnatly that doesn't work for LSB so

	 * reject these for now */

	/* Note: 32 bits word, LSB works iff

	 * tfcr/rfcr is set to CPMFCR_GBL */

	if (spi->mode & SPI_LSB_FIRST &&

	    bits_per_word > 8)

		return -EINVAL;

	if (bits_per_word <= 8)

		return bits_per_word;

	if (bits_per_word == 16 || bits_per_word == 32)

		return 8; /* pretend its 8 bits */

	return -EINVAL;

}



static int fsl_spi_setup_transfer(struct spi_device *spi,

					struct spi_transfer *t)

{
@@ -251,9 +231,6 @@ static int fsl_spi_setup_transfer(struct spi_device *spi, 
		bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,

							   mpc8xxx_spi,

							   bits_per_word);

	else

		bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,

							  bits_per_word);



	if (bits_per_word < 0)

		return bits_per_word;
@@ -371,14 +348,27 @@ static int fsl_spi_do_one_msg(struct spi_master *master, 
	 * In CPU mode, optimize large byte transfers to use larger

	 * bits_per_word values to reduce number of interrupts taken.

	 */

	if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {

	list_for_each_entry(t, &m->transfers, transfer_list) {

		if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {

			if (t->len < 256 || t->bits_per_word != 8)

				continue;

			if ((t->len & 3) == 0)

				t->bits_per_word = 32;

			else if ((t->len & 1) == 0)

				t->bits_per_word = 16;

		} else {

			/*

			 * CPM/QE uses Little Endian for words > 8

			 * so transform 16 and 32 bits words into 8 bits

			 * Unfortnatly that doesn't work for LSB so

			 * reject these for now

			 * Note: 32 bits word, LSB works iff

			 * tfcr/rfcr is set to CPMFCR_GBL

			 */

			if (m->spi->mode & SPI_LSB_FIRST && t->bits_per_word > 8)

				return -EINVAL;

			if (t->bits_per_word == 16 || t->bits_per_word == 32)

				t->bits_per_word = 8; /* pretend its 8 bits */

		}

	}
@@ -637,8 +627,14 @@ static struct spi_master * fsl_spi_probe(struct device *dev, 
	if (mpc8xxx_spi->type == TYPE_GRLIB)

		fsl_spi_grlib_probe(dev);



	if (mpc8xxx_spi->flags & SPI_CPM_MODE)

		master->bits_per_word_mask =

		(SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &

			(SPI_BPW_RANGE_MASK(4, 8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(32));

	else

		master->bits_per_word_mask =

			(SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32));



	master->bits_per_word_mask &=

		SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);



	if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)