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Commit d6001aed authored by Yongqiang Sun's avatar Yongqiang Sun Committed by Alex Deucher
Browse files

drm/amd/display: Refactor for setup periodic interrupt. 



[Why]
Current periodic interrupt start point calc in optc
is not clear.

[How]
1. DM convert delta time to lines number and dc will calculate the
   start position as per lines number and interrupt type.
2. hwss calculates the start point as per line offset.
3. optc programs vertical interrupts register as per start point
   and interrupt source.

Signed-off-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d8d2f174

drivers/gpu/drm/amd/display/dc/core/dc.c

+6 −6
Original line number Diff line number Diff line
@@ -1626,13 +1626,13 @@ static void commit_planes_do_stream_update(struct dc *dc, 
					stream_update->adjust->v_total_min,

					stream_update->adjust->v_total_max);



			if (stream_update->periodic_vsync_config && pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)

				pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(

					pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, VLINE0, &stream->periodic_vsync_config);

			if (stream_update->periodic_interrupt0 &&

					dc->hwss.setup_periodic_interrupt)

				dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE0);



			if (stream_update->enhanced_sync_config && pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)

				pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(

					pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, VLINE1, &stream->enhanced_sync_config);

			if (stream_update->periodic_interrupt1 &&

					dc->hwss.setup_periodic_interrupt)

				dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE1);



			if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||

					stream_update->vrr_infopacket ||

drivers/gpu/drm/amd/display/dc/dc_stream.h

+17 −7
Original line number Diff line number Diff line
@@ -51,9 +51,19 @@ struct freesync_context { 
	bool dummy;

};



union vline_config {

	unsigned int line_number;

	unsigned long long delta_in_ns;

enum vertical_interrupt_ref_point {

	START_V_UPDATE = 0,

	START_V_SYNC,

	INVALID_POINT



	//For now, only v_update interrupt is used.

	//START_V_BLANK,

	//START_V_ACTIVE

};



struct periodic_interrupt_config {

	enum vertical_interrupt_ref_point ref_point;

	int lines_offset;

};
@@ -106,8 +116,8 @@ struct dc_stream_state { 
	/* DMCU info */

	unsigned int abm_level;



	union vline_config periodic_vsync_config;

	union vline_config enhanced_sync_config;

	struct periodic_interrupt_config periodic_interrupt0;

	struct periodic_interrupt_config periodic_interrupt1;



	/* from core_stream struct */

	struct dc_context *ctx;
@@ -158,8 +168,8 @@ struct dc_stream_update { 
	struct dc_info_packet *hdr_static_metadata;

	unsigned int *abm_level;



	union vline_config *periodic_vsync_config;

	union vline_config *enhanced_sync_config;

	struct periodic_interrupt_config *periodic_interrupt0;

	struct periodic_interrupt_config *periodic_interrupt1;



	struct dc_crtc_timing_adjust *adjust;

	struct dc_info_packet *vrr_infopacket;

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+2 −4
Original line number Diff line number Diff line
@@ -1333,10 +1333,8 @@ static enum dc_status apply_single_controller_ctx_to_hw( 
	if (!pipe_ctx->stream->apply_seamless_boot_optimization)

		dc->hwss.enable_stream_timing(pipe_ctx, context, dc);



	if (pipe_ctx->stream_res.tg->funcs->program_vupdate_interrupt)

		pipe_ctx->stream_res.tg->funcs->program_vupdate_interrupt(

						pipe_ctx->stream_res.tg,

							&stream->timing);

	if (dc->hwss.setup_vupdate_interrupt)

		dc->hwss.setup_vupdate_interrupt(pipe_ctx);



	params.vertical_total_min = stream->adjust.v_total_min;

	params.vertical_total_max = stream->adjust.v_total_max;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+144 −1
Original line number Diff line number Diff line
@@ -2741,6 +2741,147 @@ static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx) 
			pipe_ctx->plane_res.dpp, &opt_attr);

}



/**

* apply_front_porch_workaround  TODO FPGA still need?

*

* This is a workaround for a bug that has existed since R5xx and has not been

* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.

*/

static void apply_front_porch_workaround(

	struct dc_crtc_timing *timing)

{

	if (timing->flags.INTERLACE == 1) {

		if (timing->v_front_porch < 2)

			timing->v_front_porch = 2;

	} else {

		if (timing->v_front_porch < 1)

			timing->v_front_porch = 1;

	}

}



int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)

{

	struct timing_generator *optc = pipe_ctx->stream_res.tg;

	const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;

	struct dc_crtc_timing patched_crtc_timing;

	int vesa_sync_start;

	int asic_blank_end;

	int interlace_factor;

	int vertical_line_start;



	patched_crtc_timing = *dc_crtc_timing;

	apply_front_porch_workaround(&patched_crtc_timing);



	interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;



	vesa_sync_start = patched_crtc_timing.v_addressable +

			patched_crtc_timing.v_border_bottom +

			patched_crtc_timing.v_front_porch;



	asic_blank_end = (patched_crtc_timing.v_total -

			vesa_sync_start -

			patched_crtc_timing.v_border_top)

			* interlace_factor;



	vertical_line_start = asic_blank_end -

			optc->dlg_otg_param.vstartup_start + 1;



	return vertical_line_start;

}



static void calc_vupdate_position(

		struct pipe_ctx *pipe_ctx,

		uint32_t *start_line,

		uint32_t *end_line)

{

	const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;

	int vline_int_offset_from_vupdate =

			pipe_ctx->stream->periodic_interrupt0.lines_offset;

	int vupdate_offset_from_vsync = get_vupdate_offset_from_vsync(pipe_ctx);

	int start_position;



	if (vline_int_offset_from_vupdate > 0)

		vline_int_offset_from_vupdate--;

	else if (vline_int_offset_from_vupdate < 0)

		vline_int_offset_from_vupdate++;



	start_position = vline_int_offset_from_vupdate + vupdate_offset_from_vsync;



	if (start_position >= 0)

		*start_line = start_position;

	else

		*start_line = dc_crtc_timing->v_total + start_position - 1;



	*end_line = *start_line + 2;



	if (*end_line >= dc_crtc_timing->v_total)

		*end_line = 2;

}



static void cal_vline_position(

		struct pipe_ctx *pipe_ctx,

		enum vline_select vline,

		uint32_t *start_line,

		uint32_t *end_line)

{

	enum vertical_interrupt_ref_point ref_point = INVALID_POINT;



	if (vline == VLINE0)

		ref_point = pipe_ctx->stream->periodic_interrupt0.ref_point;

	else if (vline == VLINE1)

		ref_point = pipe_ctx->stream->periodic_interrupt1.ref_point;



	switch (ref_point) {

	case START_V_UPDATE:

		calc_vupdate_position(

				pipe_ctx,

				start_line,

				end_line);

		break;

	case START_V_SYNC:

		// Suppose to do nothing because vsync is 0;

		break;

	default:

		ASSERT(0);

		break;

	}

}



static void dcn10_setup_periodic_interrupt(

		struct pipe_ctx *pipe_ctx,

		enum vline_select vline)

{

	struct timing_generator *tg = pipe_ctx->stream_res.tg;



	if (vline == VLINE0) {

		uint32_t start_line = 0;

		uint32_t end_line = 0;



		cal_vline_position(pipe_ctx, vline, &start_line, &end_line);



		tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);



	} else if (vline == VLINE1) {

		pipe_ctx->stream_res.tg->funcs->setup_vertical_interrupt1(

				tg,

				pipe_ctx->stream->periodic_interrupt1.lines_offset);

	}

}



static void dcn10_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)

{

	struct timing_generator *tg = pipe_ctx->stream_res.tg;

	int start_line = get_vupdate_offset_from_vsync(pipe_ctx);



	if (start_line < 0) {

		ASSERT(0);

		start_line = 0;

	}



	if (tg->funcs->setup_vertical_interrupt2)

		tg->funcs->setup_vertical_interrupt2(tg, start_line);

}



static const struct hw_sequencer_funcs dcn10_funcs = {

	.program_gamut_remap = program_gamut_remap,

	.init_hw = dcn10_init_hw,
@@ -2790,7 +2931,9 @@ static const struct hw_sequencer_funcs dcn10_funcs = { 
	.set_cursor_attribute = dcn10_set_cursor_attribute,

	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,

	.disable_stream_gating = NULL,

	.enable_stream_gating = NULL

	.enable_stream_gating = NULL,

	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,

	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt

};

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

+2 −0
Original line number Diff line number Diff line
@@ -81,4 +81,6 @@ struct pipe_ctx *find_top_pipe_for_stream( 
		struct dc_state *context,

		const struct dc_stream_state *stream);



int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);



#endif /* __DC_HWSS_DCN10_H__ */