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Commit d5e72aa1 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'tegra-for-4.18-dt-bindings' of... 

Merge tag 'tegra-for-4.18-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt

dt-bindings: tegra: Changes for v4.18-rc1

This contains the device tree bindings updates for the memory controller
hot resets that are implemented by driver patches in a different branch.

* tag 'tegra-for-4.18-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux

:
  dt-bindings: Relocate Tegra20 memory controller bindings
  dt-bindings: arm: tegra: Document #reset-cells property of the Tegra20 MC
  dt-bindings: memory: tegra: Document #reset-cells property of the Tegra30 MC
  dt-bindings: arm: tegra: Remove duplicated Tegra30+ MC binding

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents ff9da3ce eb8f53b6

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt

deleted100644 → 0
+0 −18
Original line number Diff line number Diff line 
NVIDIA Tegra30 MC(Memory Controller)



Required properties:

- compatible : "nvidia,tegra30-mc"

- reg : Should contain 4 register ranges(address and length); see the

  example below. Note that the MC registers are interleaved with the

  SMMU registers, and hence must be represented as multiple ranges.

- interrupts : Should contain MC General interrupt.



Example:

	memory-controller {

		compatible = "nvidia,tegra30-mc";

		reg = <0x7000f000 0x010

		       0x7000f03c 0x1b4

		       0x7000f200 0x028

		       0x7000f284 0x17c>;

		interrupts = <0 77 0x04>;

	};

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt→Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt

+11 −1
Original line number Diff line number Diff line
@@ -6,11 +6,21 @@ Required properties: 
  example below. Note that the MC registers are interleaved with the

  GART registers, and hence must be represented as multiple ranges.

- interrupts : Should contain MC General interrupt.

- #reset-cells : Should be 1. This cell represents memory client module ID.

  The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>

  or in the TRM documentation.



Example:

	memory-controller@7000f000 {

	mc: memory-controller@7000f000 {

		compatible = "nvidia,tegra20-mc";

		reg = <0x7000f000 0x024

		       0x7000f03c 0x3c4>;

		interrupts = <0 77 0x04>;

		#reset-cells = <1>;

	};



	video-codec@6001a000 {

		compatible = "nvidia,tegra20-vde";

		...

		resets = <&mc TEGRA20_MC_RESET_VDE>;

	};

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt

+5 −0
Original line number Diff line number Diff line
@@ -12,6 +12,9 @@ Required properties: 
- clock-names: Must include the following entries:

  - mc: the module's clock input

- interrupts: The interrupt outputs from the controller.

- #reset-cells : Should be 1. This cell represents memory client module ID.

  The assignments may be found in header file <dt-bindings/memory/tegra30-mc.h>

  or in the TRM documentation.



Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210:

- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
@@ -72,12 +75,14 @@ Example SoC include file: 
		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;



		#iommu-cells = <1>;

		#reset-cells = <1>;

	};



	sdhci@700b0000 {

		compatible = "nvidia,tegra124-sdhci";

		...

		iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;

		resets = <&mc TEGRA124_MC_RESET_SDMMC1>;

	};

};