Merge "asoc: codecs: Do not update VA clk muxsel register" (d5e44c9b) · Commits · e / devices / android_kernel_fairphone_FP5

asoc/codecs/bolero/bolero-clk-rsc.c

+38 −13

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2019, The Linux Foundation. All rights reserved.
		* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
		*/

		#include <linux/of_platform.h>
		@@ -247,10 +247,13 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv,

		if (enable) {
		if (priv->clk_cnt[clk_id] == 0) {
		ret = bolero_clk_rsc_mux0_clk_request(priv, default_clk_id,
		if (clk_id != VA_CORE_CLK) {
		ret = bolero_clk_rsc_mux0_clk_request(priv,
		default_clk_id,
		true);
		if (ret < 0)
		goto done;
		}

		ret = clk_prepare_enable(priv->clk[clk_id]);
		if (ret < 0) {
		@@ -268,10 +271,20 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv,
		goto err_npl_clk;
		}
		}

		/*
		* Temp SW workaround to address a glitch issue of
		* VA GFMux instance responsible for switching from
		* TX MCLK to VA MCLK. This configuration would be taken
		* care in DSP itself
		*/
		if (clk_id != VA_CORE_CLK) {
		iowrite32(0x1, clk_muxsel);
		bolero_clk_rsc_mux0_clk_request(priv, default_clk_id,
		bolero_clk_rsc_mux0_clk_request(priv,
		default_clk_id,
		false);
		}
		}
		priv->clk_cnt[clk_id]++;
		} else {
		if (priv->clk_cnt[clk_id] <= 0) {
		@@ -282,28 +295,40 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv,
		}
		priv->clk_cnt[clk_id]--;
		if (priv->clk_cnt[clk_id] == 0) {
		if (clk_id != VA_CORE_CLK) {
		ret = bolero_clk_rsc_mux0_clk_request(priv,
		default_clk_id, true);

		if (!ret)
		if (!ret) {
		/*
		* Temp SW workaround to address a glitch issue
		* of VA GFMux instance responsible for
		* switching from TX MCLK to VA MCLK.
		* This configuration would be taken
		* care in DSP itself.
		*/
		iowrite32(0x0, clk_muxsel);

		}
		}
		if (priv->clk[clk_id + NPL_CLK_OFFSET])
		clk_disable_unprepare(
		priv->clk[clk_id + NPL_CLK_OFFSET]);
		clk_disable_unprepare(priv->clk[clk_id]);

		if (clk_id != VA_CORE_CLK) {
		if (!ret)
		bolero_clk_rsc_mux0_clk_request(priv,
		default_clk_id, false);
		}
		}
		}
		return ret;

		err_npl_clk:
		clk_disable_unprepare(priv->clk[clk_id]);

		err_clk:
		if (clk_id != VA_CORE_CLK)
		bolero_clk_rsc_mux0_clk_request(priv, default_clk_id, false);
		done:
		return ret;