Commit d50a9e1b authored Sep 19, 2015 by Hans de Goede Committed by Linus Walleij Oct 02, 2015

pinctrl: sun5i: Fix a10s pwm1 pinctrl mapping



The comment for PG14 mux setting 3 already correctly states that this
muxes PG13 to pwm1, but the text ascociated with it said uart3, fix this.

Note that we use "pwm" rather then "pwm1" to be consistent with pwm0
where the mux setting is also simply called "pwm" and to be consistent
with sun4i/sun7i which do the same.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

parent 1f93e4a9

drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -653,7 +653,7 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
		SUNXI_FUNCTION(0x0, "gpio_in"),
		SUNXI_FUNCTION(0x1, "gpio_out"),
		SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
		SUNXI_FUNCTION(0x3, "uart3"), /* PWM1 */
		SUNXI_FUNCTION(0x3, "pwm"), /* PWM1 */
		SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
		SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
		};