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Commit d507cd66 authored by Takashi Iwai's avatar Takashi Iwai
Browse files

ALSA: hda - Enable sync_write workaround for AMD generically 



The workaround for AMD chipset via sync_write flag seems needed for
machines with Realtek codecs.  So, it's better to activate it
generically in hda_intel.c from the beginning.

Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
parent 0da26922

sound/pci/hda/hda_intel.c

+11 −0
Original line number Diff line number Diff line
@@ -1447,6 +1447,17 @@ static int __devinit azx_codec_create(struct azx *chip, const char *model) 
		}

	}



	/* AMD chipsets often cause the communication stalls upon certain

	 * sequence like the pin-detection.  It seems that forcing the synced

	 * access works around the stall.  Grrr...

	 */

	if (chip->pci->vendor == PCI_VENDOR_ID_AMD ||

	    chip->pci->vendor == PCI_VENDOR_ID_ATI) {

		snd_printk(KERN_INFO SFX "Enable sync_write for AMD chipset\n");

		chip->bus->sync_write = 1;

		chip->bus->allow_bus_reset = 1;

	}



	/* Then create codec instances */

	for (c = 0; c < max_slots; c++) {

		if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {

sound/pci/hda/patch_sigmatel.c

+0 −16
Original line number Diff line number Diff line
@@ -5449,13 +5449,6 @@ static int patch_stac92hd83xxx(struct hda_codec *codec) 
	spec->multiout.dac_nids = spec->dac_nids;

	spec->init = stac92hd83xxx_core_init;



	if (codec->bus->pci && codec->bus->pci->vendor == PCI_VENDOR_ID_AMD) {

		snd_printk(KERN_INFO "idt92hd83xxx: "

			   "Enable sync_write for AMD chipset\n");

		codec->bus->sync_write = 1;

		codec->bus->allow_bus_reset = 1;

	}



	spec->board_config = snd_hda_check_board_config(codec,

							STAC_92HD83XXX_MODELS,

							stac92hd83xxx_models,
@@ -5736,15 +5729,6 @@ static int patch_stac92hd71bxx(struct hda_codec *codec) 
	if (get_wcaps(codec, 0xa) & AC_WCAP_IN_AMP)

		snd_hda_sequence_write_cache(codec, unmute_init);



	/* Some HP machines seem to have unstable codec communications

	 * especially with ATI fglrx driver.  For recovering from the

	 * CORB/RIRB stall, allow the BUS reset and keep always sync

	 */

	if (spec->board_config == STAC_HP_DV5) {

		codec->bus->sync_write = 1;

		codec->bus->allow_bus_reset = 1;

	}



	spec->aloopback_ctl = stac92hd71bxx_loopback;

	spec->aloopback_mask = 0x50;

	spec->aloopback_shift = 0;