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Commit d4eb7653 authored by Joseph Lo's avatar Joseph Lo Committed by Thierry Reding
Browse files

arm64: tegra: Enable DFLL clock on Smaug 



Enable DFLL clock for Smaug board.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Acked-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent f9c8bcc0

arch/arm64/boot/dts/nvidia/tegra210-smaug.dts

+12 −0
Original line number Original line Diff line number Diff line
@@ -1698,6 +1698,18 @@ 
		status = "okay";

		status = "okay";

	};

	};





	clock@70110000 {

		status = "okay";

		nvidia,cf = <6>;

		nvidia,ci = <0>;

		nvidia,cg = <2>;

		nvidia,droop-ctrl = <0x00000f00>;

		nvidia,force-mode = <1>;

		nvidia,i2c-fs-rate = <400000>;

		nvidia,sample-rate = <12500>;

		vdd-cpu-supply = <&max77621_cpu>;

	};



	aconnect@702c0000 {

	aconnect@702c0000 {

		status = "okay";

		status = "okay";