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Commit d4c2456a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc 

Pull powerpc fixes from Benjamin Herrenschmidt:
 "Some more P8 related bits, a bunch of fixes for our P7+/P8 HW crypto
  drivers, some added workarounds for those radeons that don't do proper
  64-bit MSIs and a couple of other trivialities by myself."

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
  powerpc/pseries: Make 32-bit MSI quirk work on systems lacking firmware support
  powerpc/powernv: Build a zImage.epapr
  powerpc: Make radeon 32-bit MSI quirk work on powernv
  powerpc: Context switch more PMU related SPRs
  powerpc/powernv: Fix condition for when to invalidate the TCE cache
  powerpc/pci: Fix bogus message at boot about empty memory resources
  powerpc: Fix TLB cleanup at boot on POWER8
  drivers/crypto/nx: Fixes for multiple races and issues
parents eb3d3390 f1dd1531

arch/powerpc/include/asm/pci-bridge.h

+2 −0
Original line number Diff line number Diff line
@@ -174,6 +174,8 @@ struct pci_dn { 
/* Get the pointer to a device_node's pci_dn */

#define PCI_DN(dn)	((struct pci_dn *) (dn)->data)



extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);



extern void * update_dn_pci_info(struct device_node *dn, void *data);



static inline int pci_device_from_OF_node(struct device_node *np,

arch/powerpc/include/asm/processor.h

+6 −0
Original line number Diff line number Diff line
@@ -284,6 +284,12 @@ struct thread_struct { 
	unsigned long	ebbrr;

	unsigned long	ebbhr;

	unsigned long	bescr;

	unsigned long	siar;

	unsigned long	sdar;

	unsigned long	sier;

	unsigned long	mmcr0;

	unsigned long	mmcr2;

	unsigned long	mmcra;

#endif

};

arch/powerpc/kernel/asm-offsets.c

+6 −0
Original line number Diff line number Diff line
@@ -127,6 +127,12 @@ int main(void) 
	DEFINE(THREAD_BESCR, offsetof(struct thread_struct, bescr));

	DEFINE(THREAD_EBBHR, offsetof(struct thread_struct, ebbhr));

	DEFINE(THREAD_EBBRR, offsetof(struct thread_struct, ebbrr));

	DEFINE(THREAD_SIAR, offsetof(struct thread_struct, siar));

	DEFINE(THREAD_SDAR, offsetof(struct thread_struct, sdar));

	DEFINE(THREAD_SIER, offsetof(struct thread_struct, sier));

	DEFINE(THREAD_MMCR0, offsetof(struct thread_struct, mmcr0));

	DEFINE(THREAD_MMCR2, offsetof(struct thread_struct, mmcr2));

	DEFINE(THREAD_MMCRA, offsetof(struct thread_struct, mmcra));

#endif

#ifdef CONFIG_PPC_TRANSACTIONAL_MEM

	DEFINE(PACATMSCRATCH, offsetof(struct paca_struct, tm_scratch));

arch/powerpc/kernel/cpu_setup_power.S

+6 −2
Original line number Diff line number Diff line
@@ -135,8 +135,12 @@ __init_HFSCR: 
	blr



__init_TLB:

	/* Clear the TLB */

	li	r6,128

	/*

	 * Clear the TLB using the "IS 3" form of tlbiel instruction

	 * (invalidate by congruence class). P7 has 128 CCs, P8 has 512

	 * so we just always do 512

	 */

	li	r6,512

	mtctr	r6

	li	r7,0xc00	/* IS field = 0b11 */

	ptesync

arch/powerpc/kernel/entry_64.S

+28 −0
Original line number Diff line number Diff line
@@ -465,6 +465,20 @@ BEGIN_FTR_SECTION 
	std	r0, THREAD_EBBHR(r3)

	mfspr	r0, SPRN_EBBRR

	std	r0, THREAD_EBBRR(r3)



	/* PMU registers made user read/(write) by EBB */

	mfspr	r0, SPRN_SIAR

	std	r0, THREAD_SIAR(r3)

	mfspr	r0, SPRN_SDAR

	std	r0, THREAD_SDAR(r3)

	mfspr	r0, SPRN_SIER

	std	r0, THREAD_SIER(r3)

	mfspr	r0, SPRN_MMCR0

	std	r0, THREAD_MMCR0(r3)

	mfspr	r0, SPRN_MMCR2

	std	r0, THREAD_MMCR2(r3)

	mfspr	r0, SPRN_MMCRA

	std	r0, THREAD_MMCRA(r3)

END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)

#endif
@@ -560,6 +574,20 @@ BEGIN_FTR_SECTION 
	ld	r0, THREAD_EBBRR(r4)

	mtspr	SPRN_EBBRR, r0



	/* PMU registers made user read/(write) by EBB */

	ld	r0, THREAD_SIAR(r4)

	mtspr	SPRN_SIAR, r0

	ld	r0, THREAD_SDAR(r4)

	mtspr	SPRN_SDAR, r0

	ld	r0, THREAD_SIER(r4)

	mtspr	SPRN_SIER, r0

	ld	r0, THREAD_MMCR0(r4)

	mtspr	SPRN_MMCR0, r0

	ld	r0, THREAD_MMCR2(r4)

	mtspr	SPRN_MMCR2, r0

	ld	r0, THREAD_MMCRA(r4)

	mtspr	SPRN_MMCRA, r0



	ld	r0,THREAD_TAR(r4)

	mtspr	SPRN_TAR,r0

END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)