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Commit d4a451d5 authored by Christoph Hellwig's avatar Christoph Hellwig
Browse files

arch: remove the ARCH_PHYS_ADDR_T_64BIT config symbol



Instead select the PHYS_ADDR_T_64BIT for 32-bit architectures that need a
64-bit phys_addr_t type directly.

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Acked-by: default avatarJames Hogan <jhogan@kernel.org>
parent f616ab59
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+1 −3
Original line number Diff line number Diff line
@@ -453,13 +453,11 @@ config ARC_HAS_PAE40
	default n
	depends on ISA_ARCV2
	select HIGHMEM
	select PHYS_ADDR_T_64BIT
	help
	  Enable access to physical memory beyond 4G, only supported on
	  ARC cores with 40 bit Physical Addressing support

config ARCH_PHYS_ADDR_T_64BIT
	def_bool ARC_HAS_PAE40

config ARCH_DMA_ADDR_T_64BIT
	bool

+1 −1
Original line number Diff line number Diff line
@@ -754,7 +754,7 @@ int __init arm_add_memory(u64 start, u64 size)
	else
		size -= aligned_start - start;

#ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
#ifndef CONFIG_PHYS_ADDR_T_64BIT
	if (aligned_start > ULONG_MAX) {
		pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n",
			(long long)start);
+1 −3
Original line number Diff line number Diff line
@@ -661,6 +661,7 @@ config ARM_LPAE
	bool "Support for the Large Physical Address Extension"
	depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
		!CPU_32v4 && !CPU_32v3
	select PHYS_ADDR_T_64BIT
	help
	  Say Y if you have an ARMv7 processor supporting the LPAE page
	  table format and you would like to access memory beyond the
@@ -673,9 +674,6 @@ config ARM_PV_FIXUP
	def_bool y
	depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE

config ARCH_PHYS_ADDR_T_64BIT
	def_bool ARM_LPAE

config ARCH_DMA_ADDR_T_64BIT
	bool

+0 −3
Original line number Diff line number Diff line
@@ -151,9 +151,6 @@ config ARM64
config 64BIT
	def_bool y

config ARCH_PHYS_ADDR_T_64BIT
	def_bool y

config MMU
	def_bool y

+6 −9
Original line number Diff line number Diff line
@@ -131,7 +131,7 @@ config MIPS_GENERIC

config MIPS_ALCHEMY
	bool "Alchemy processor based machines"
	select ARCH_PHYS_ADDR_T_64BIT
	select PHYS_ADDR_T_64BIT
	select CEVT_R4K
	select CSRC_R4K
	select IRQ_MIPS_CPU
@@ -889,7 +889,7 @@ config CAVIUM_OCTEON_SOC
	bool "Cavium Networks Octeon SoC based boards"
	select CEVT_R4K
	select ARCH_HAS_PHYS_TO_DMA
	select ARCH_PHYS_ADDR_T_64BIT
	select PHYS_ADDR_T_64BIT
	select DMA_COHERENT
	select SYS_SUPPORTS_64BIT_KERNEL
	select SYS_SUPPORTS_BIG_ENDIAN
@@ -935,7 +935,7 @@ config NLM_XLR_BOARD
	select SWAP_IO_SPACE
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_64BIT_KERNEL
	select ARCH_PHYS_ADDR_T_64BIT
	select PHYS_ADDR_T_64BIT
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_HIGHMEM
	select DMA_COHERENT
@@ -961,7 +961,7 @@ config NLM_XLP_BOARD
	select HW_HAS_PCI
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_64BIT_KERNEL
	select ARCH_PHYS_ADDR_T_64BIT
	select PHYS_ADDR_T_64BIT
	select GPIOLIB
	select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -1101,7 +1101,7 @@ config FW_CFE
	bool

config ARCH_DMA_ADDR_T_64BIT
	def_bool (HIGHMEM && ARCH_PHYS_ADDR_T_64BIT) || 64BIT
	def_bool (HIGHMEM && PHYS_ADDR_T_64BIT) || 64BIT

config ARCH_SUPPORTS_UPROBES
	bool
@@ -1766,7 +1766,7 @@ config CPU_MIPS32_R5_XPA
	depends on SYS_SUPPORTS_HIGHMEM
	select XPA
	select HIGHMEM
	select ARCH_PHYS_ADDR_T_64BIT
	select PHYS_ADDR_T_64BIT
	default n
	help
	  Choose this option if you want to enable the Extended Physical
@@ -2398,9 +2398,6 @@ config SB1_PASS_2_1_WORKAROUNDS
	default y


config ARCH_PHYS_ADDR_T_64BIT
       bool

choice
	prompt "SmartMIPS or microMIPS ASE support"

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