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Commit d4993e19 authored by Yash Shah's avatar Yash Shah Committed by David S. Miller
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macb: bindings doc: add sifive fu540-c000 binding 



Add the compatibility string documentation for SiFive FU540-C0000
interface.
On the FU540, this driver also needs to read and write registers in a
management IP block that monitors or drives boundary signals for the
GEMGXL IP block that are not directly mapped to GEMGXL registers.
Therefore, add additional range to "reg" property for SiFive GEMGXL
management IP registers.

Signed-off-by: default avatarYash Shah <yash.shah@sifive.com>
Reviewed-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d75d5f97

Documentation/devicetree/bindings/net/macb.txt

+3 −0
Original line number Diff line number Diff line
@@ -15,8 +15,11 @@ Required properties: 
  Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs.

  Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.

  Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.

  Use "sifive,fu540-macb" for SiFive FU540-C000 SoC.

  Or the generic form: "cdns,emac".

- reg: Address and length of the register set for the device

	For "sifive,fu540-macb", second range is required to specify the

	address and length of the registers for GEMGXL Management block.

- interrupts: Should contain macb interrupt

- phy-mode: See ethernet.txt file in the same directory.

- clock-names: Tuple listing input clock names.