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Commit d481d5ae authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add eMMC, SD card support for shima"

parents 61d49887 10b8bbed

qcom/shima-pinctrl.dtsi

+102 −0
Original line number Diff line number Diff line
@@ -1397,6 +1397,108 @@ 
			};

		};



		sdc1_on: sdc1_on {

			clk {

				pins = "sdc1_clk";

				bias-disable;

				drive-strength = <16>;

			};



			cmd {

				pins = "sdc1_cmd";

				bias-pull-up;

				drive-strength = <10>;

			};



			data {

				pins = "sdc1_data";

				bias-pull-up;

				drive-strength = <10>;

			};



			rclk {

				pins = "sdc1_rclk";

				bias-pull-down;

			};

		};



		sdc1_off: sdc1_off {

			clk {

				pins = "sdc1_clk";

				bias-disable;

				drive-strength = <2>;

			};



			cmd {

				pins = "sdc1_cmd";

				bias-pull-up;

				drive-strength = <2>;

			};



			data {

				pins = "sdc1_data";

				bias-pull-up;

				drive-strength = <2>;

			};



			rclk {

				pins = "sdc1_rclk";

				bias-pull-down;

			};

		};



		sdc2_on: sdc2_on {

			clk {

				pins = "sdc2_clk";

				bias-disable;

				drive-strength = <16>;

			};



			cmd {

				pins = "sdc2_cmd";

				bias-pull-up;

				drive-strength = <10>;

			};



			data {

				pins = "sdc2_data";

				bias-pull-up;

				drive-strength = <10>;

			};



			sd-cd {

				pins = "gpio92";

				bias-pull-up;

				drive-strength = <2>;

			};

		};



		sdc2_off: sdc2_off {

			clk {

				pins = "sdc2_clk";

				bias-disable;

				drive-strength = <2>;

			};



			cmd {

				pins = "sdc2_cmd";

				bias-pull-up;

				drive-strength = <2>;

			};



			data {

				pins = "sdc2_data";

				bias-pull-up;

				drive-strength = <2>;

			};



			sd-cd {

				pins = "gpio92";

				bias-disable;

				drive-strength = <2>;

			};

		};



		cci0_active: cci0_active {

			mux {

				/* CLK, DATA */

qcom/shima-rumi.dtsi

+41 −1
Original line number Diff line number Diff line 
#include <dt-bindings/clock/qcom,gcc-shima.h>



#include <dt-bindings/gpio/gpio.h>

&soc {

	timer {

		clock-frequency = <5000000>;
@@ -96,6 +96,46 @@ 
	status = "ok";

};



&sdhc_1 {

	status = "ok";



	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&sdc1_on>;

	pinctrl-1 = <&sdc1_off>;



	vdd-supply = <&pm8350_l7>;

	qcom,vdd-voltage-level = <2960000 2960000>;

	qcom,vdd-current-level = <0 570000>;



	vdd-io-supply = <&pm8350_s10>;

	qcom,vdd-io-always-on;

	qcom,vdd-io-lpm-sup;

	qcom,vdd-io-voltage-level = <1800000 1800000>;

	qcom,vdd-io-current-level = <0 325000>;



	cap-mmc-highspeed;

};



&sdhc_2 {

	status = "ok";



	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&sdc2_on>;

	pinctrl-1 = <&sdc2_off>;



	vdd-supply = <&pm8350c_l9>;

	qcom,vdd-voltage-level = <2960000 2960000>;

	qcom,vdd-current-level = <0 800000>;



	vdd-io-supply = <&pm8350c_l6>;

	qcom,vdd-io-voltage-level = <2960000 2960000>;

	qcom,vdd-io-current-level = <0 22000>;



	cap-sd-highspeed;



	cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;

};



/* Debug UART console */

&qupv3_se13_2uart {

	qcom,rumi_platform;

qcom/shima.dtsi

+46 −0
Original line number Diff line number Diff line
@@ -26,6 +26,8 @@ 


	aliases {

			ufshc1 = &ufshc_mem; /* Embedded UFS Slot */

			sdhc1 = &sdhc_1; /*SDC1 eMMC slot*/

			sdhc2 = &sdhc_2; /* SDC2 SD card slot */

		};



	cpus {
@@ -1170,6 +1172,50 @@ 
		 status = "disabled";

	};



	sdhc_1: sdhci@7C4000 {

		compatible = "qcom,sdhci-msm-v5";

		reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>;

		reg-names = "hc_mem", "cqhci_mem";



		iommus = <&apps_smmu 0xc0 0x0>;

		dma-coherent;

		qcom,iommu-dma = "bypass";



		interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "hc_irq", "pwr_irq";



		clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;

		clock-names = "core", "iface";



		bus-width = <8>;

		non-removable;

		supports-cqe;



		status = "disabled";

	};



	sdhc_2: sdhci@8804000 {

		compatible = "qcom,sdhci-msm-v5";

		reg = <0x08804000 0x1000>;

		reg-names = "hc_mem";



		interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "hc_irq", "pwr_irq";



		clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;

		clock-names = "core", "iface";



		bus-width = <4>;



		iommus = <&apps_smmu 0x4a0 0x0>;

		dma-coherent;

		qcom,iommu-dma = "bypass";



		status = "disabled";

	};



	apps_rsc: rsc@18200000 {

		label = "apps_rsc";

		compatible = "qcom,rpmh-rsc";