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Commit d47fc7e8 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Update VideoCC node and Multimedia GDSC's for YUPIK"

parents d19d47f9 c1846e80

qcom/yupik-rumi.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -174,3 +174,7 @@ 
	clocks = <&bi_tcxo>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,

		<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>;

};



&videocc {

	clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>, <&gcc GCC_VIDEO_AHB_CLK>;

};

qcom/yupik.dtsi

+34 −11
Original line number Diff line number Diff line
@@ -755,8 +755,13 @@ 
	};



	videocc: clock-controller@aaf0000 {

		compatible = "qcom,dummycc";

		clock-output-names = "videocc_clocks";

		compatible = "qcom,yupik-videocc", "syscon";

		reg = <0xaaf0000 0x10000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,

			<&sleep_clk>, <&gcc GCC_VIDEO_AHB_CLK>;

		clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "cfg_ahb";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -1967,41 +1972,55 @@ 
};



&cam_cc_titan_top_gdsc {

	compatible = "regulator-fixed";

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_CX_LEVEL>;

	reg = <0xad0c194 0x4>;

	status = "ok";

};



&cam_cc_bps_gdsc {

	compatible = "regulator-fixed";

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_CX_LEVEL>;

	qcom,support-hw-trigger;

	status = "ok";

};



&cam_cc_ife_0_gdsc {

	compatible = "regulator-fixed";

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_CX_LEVEL>;

	status = "ok";

};



&cam_cc_ife_1_gdsc {

	compatible = "regulator-fixed";

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_CX_LEVEL>;

	status = "ok";

};



&cam_cc_ife_2_gdsc {

	compatible = "regulator-fixed";

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_CX_LEVEL>;

	status = "ok";

};



&cam_cc_ipe_0_gdsc {

	compatible = "regulator-fixed";

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_CX_LEVEL>;

	qcom,support-hw-trigger;

	status = "ok";

};



&disp_cc_mdss_core_gdsc {

	compatible = "regulator-fixed";

	reg = <0xaf01004 0x4>;

	clocks = <&gcc GCC_DISP_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_CX_LEVEL>;

	qcom,support-hw-trigger;

	status = "ok";

};
@@ -2024,14 +2043,18 @@ 
};



&video_cc_mvs0_gdsc {

	compatible = "regulator-fixed";

	reg = <0xaaf3004 0x4>;

	clocks = <&gcc GCC_VIDEO_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_CX_LEVEL>;

	qcom,support-hw-trigger;

	status = "ok";

};



&video_cc_mvsc_gdsc {

	compatible = "regulator-fixed";

	clocks = <&gcc GCC_VIDEO_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_CX_LEVEL>;

	status = "ok";

};