Loading drivers/interconnect/qcom/scshrike.c +5 −5 Original line number Diff line number Diff line Loading @@ -682,7 +682,7 @@ static struct qcom_icc_node qhm_gemnoc_cfg = { static struct qcom_icc_qosbox qnm_cmpnoc_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 2, .offsets = { 0x56400, 0x56480 }, .offsets = { 0x57000, 0x57080 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, Loading @@ -704,7 +704,7 @@ static struct qcom_icc_node qnm_cmpnoc = { static struct qcom_icc_qosbox qnm_gpu_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 4, .offsets = { 0x56500, 0x56580, 0x56600, 0x56680 }, .offsets = { 0x57100, 0x57180, 0x57200, 0x57280 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, Loading @@ -725,7 +725,7 @@ static struct qcom_icc_node qnm_gpu = { static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 2, .offsets = { 0x56700, 0x56780 }, .offsets = { 0x57300, 0x57380 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, Loading Loading @@ -788,7 +788,7 @@ static struct qcom_icc_node qnm_pcie = { static struct qcom_icc_qosbox qnm_snoc_gc_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x56800 }, .offsets = { 0x57400 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, Loading Loading @@ -830,7 +830,7 @@ static struct qcom_icc_node qnm_snoc_sf = { static struct qcom_icc_qosbox qxm_ecc_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 2, .offsets = { 0x60a00, 0x60a80 }, .offsets = { 0x57500, 0x57580 }, .config = &(struct qos_config) { .prio = 4, .urg_fwd = 1, Loading Loading
drivers/interconnect/qcom/scshrike.c +5 −5 Original line number Diff line number Diff line Loading @@ -682,7 +682,7 @@ static struct qcom_icc_node qhm_gemnoc_cfg = { static struct qcom_icc_qosbox qnm_cmpnoc_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 2, .offsets = { 0x56400, 0x56480 }, .offsets = { 0x57000, 0x57080 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, Loading @@ -704,7 +704,7 @@ static struct qcom_icc_node qnm_cmpnoc = { static struct qcom_icc_qosbox qnm_gpu_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 4, .offsets = { 0x56500, 0x56580, 0x56600, 0x56680 }, .offsets = { 0x57100, 0x57180, 0x57200, 0x57280 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, Loading @@ -725,7 +725,7 @@ static struct qcom_icc_node qnm_gpu = { static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 2, .offsets = { 0x56700, 0x56780 }, .offsets = { 0x57300, 0x57380 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, Loading Loading @@ -788,7 +788,7 @@ static struct qcom_icc_node qnm_pcie = { static struct qcom_icc_qosbox qnm_snoc_gc_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x56800 }, .offsets = { 0x57400 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, Loading Loading @@ -830,7 +830,7 @@ static struct qcom_icc_node qnm_snoc_sf = { static struct qcom_icc_qosbox qxm_ecc_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 2, .offsets = { 0x60a00, 0x60a80 }, .offsets = { 0x57500, 0x57580 }, .config = &(struct qos_config) { .prio = 4, .urg_fwd = 1, Loading