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Commit d43c6e80 authored by Jan Beulich's avatar Jan Beulich Committed by Linus Torvalds
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[PATCH] i386: move SIMD initialization 



Move some code unrelated to any dealing with hardware bugs from i386's
bugs.h to a more logical place.

Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent e43d674f

arch/i386/kernel/traps.c

+22 −0
Original line number Diff line number Diff line
@@ -1098,6 +1098,28 @@ void __init trap_init(void) 
#endif

	set_trap_gate(19,&simd_coprocessor_error);



	if (cpu_has_fxsr) {

		/*

		 * Verify that the FXSAVE/FXRSTOR data will be 16-byte aligned.

		 * Generates a compile-time "error: zero width for bit-field" if

		 * the alignment is wrong.

		 */

		struct fxsrAlignAssert {

			int _:!(offsetof(struct task_struct,

					thread.i387.fxsave) & 15);

		};



		printk(KERN_INFO "Enabling fast FPU save and restore... ");

		set_in_cr4(X86_CR4_OSFXSR);

		printk("done.\n");

	}

	if (cpu_has_xmm) {

		printk(KERN_INFO "Enabling unmasked SIMD FPU exception "

				"support... ");

		set_in_cr4(X86_CR4_OSXMMEXCPT);

		printk("done.\n");

	}



	set_system_gate(SYSCALL_VECTOR,&system_call);



	/*

include/asm-i386/bugs.h

+1 −22
Original line number Diff line number Diff line
@@ -8,9 +8,6 @@ 
 *        <rreilova@ececs.uc.edu>

 *	- Channing Corn (tests & fixes),

 *	- Andrew D. Balsa (code cleanup).

 *

 *  Pentium III FXSR, SSE support

 *	Gareth Hughes <gareth@valinux.com>, May 2000

 */



/*
@@ -76,25 +73,7 @@ static void __init check_fpu(void) 
		return;

	}



/* Enable FXSR and company _before_ testing for FP problems. */

	/*

	 * Verify that the FXSAVE/FXRSTOR data will be 16-byte aligned.

	 */

	if (offsetof(struct task_struct, thread.i387.fxsave) & 15) {

		extern void __buggy_fxsr_alignment(void);

		__buggy_fxsr_alignment();

	}

	if (cpu_has_fxsr) {

		printk(KERN_INFO "Enabling fast FPU save and restore... ");

		set_in_cr4(X86_CR4_OSFXSR);

		printk("done.\n");

	}

	if (cpu_has_xmm) {

		printk(KERN_INFO "Enabling unmasked SIMD FPU exception support... ");

		set_in_cr4(X86_CR4_OSXMMEXCPT);

		printk("done.\n");

	}



/* trap_init() enabled FXSR and company _before_ testing for FP problems here. */

	/* Test for the divl bug.. */

	__asm__("fninit\n\t"

		"fldl %1\n\t"