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Commit d4362225 authored by Ping Gao's avatar Ping Gao Committed by Zhenyu Wang
Browse files

drm/i915/gvt: update misc ctl regs base on stepping info 



Misc ctl related registers are for WA purpose, should detect the
stepping info first before updating HW value.

Signed-off-by: default avatarPing Gao <ping.a.gao@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent f24940e0

drivers/gpu/drm/i915/gvt/handlers.c

+6 −5
Original line number Diff line number Diff line
@@ -1278,19 +1278,20 @@ static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, 
	switch (offset) {

	case 0x4ddc:

		vgpu_vreg(vgpu, offset) = 0x8000003c;

		/* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */

		if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER))

			I915_WRITE(reg, vgpu_vreg(vgpu, offset));

		break;

	case 0x42080:

		vgpu_vreg(vgpu, offset) = 0x8000;

		/* WaCompressedResourceDisplayNewHashMode:skl */

		if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER))

			I915_WRITE(reg, vgpu_vreg(vgpu, offset));

		break;

	default:

		return -EINVAL;

	}



	/**

	 * TODO: need detect stepping info after gvt contain such information

	 * 0x4ddc enabled after C0, 0x42080 enabled after E0.

	 */

	I915_WRITE(reg, vgpu_vreg(vgpu, offset));

	return 0;

}