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Commit d42281b6 authored by Jeremy Linton's avatar Jeremy Linton Committed by Will Deacon
Browse files

arm64: Always enable ssb vulnerability detection 



Ensure we are always able to detect whether or not the CPU is affected
by SSB, so that we can later advertise this to userspace.

Signed-off-by: default avatarJeremy Linton <jeremy.linton@arm.com>
Reviewed-by: default avatarAndre Przywara <andre.przywara@arm.com>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Tested-by: default avatarStefan Wahren <stefan.wahren@i2se.com>
[will: Use IS_ENABLED instead of #ifdef]
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent d2532e27

arch/arm64/include/asm/cpufeature.h

+0 −4
Original line number Diff line number Diff line
@@ -638,11 +638,7 @@ static inline int arm64_get_ssbd_state(void) 
#endif

}



#ifdef CONFIG_ARM64_SSBD

void arm64_set_ssbd_mitigation(bool state);

#else

static inline void arm64_set_ssbd_mitigation(bool state) {}

#endif



extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);

arch/arm64/kernel/cpu_errata.c

+5 −4
Original line number Diff line number Diff line
@@ -275,7 +275,6 @@ static int detect_harden_bp_fw(void) 
	return 1;

}



#ifdef CONFIG_ARM64_SSBD

DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);



int ssbd_state __read_mostly = ARM64_SSBD_KERNEL;
@@ -348,6 +347,11 @@ void __init arm64_enable_wa2_handling(struct alt_instr *alt, 


void arm64_set_ssbd_mitigation(bool state)

{

	if (!IS_ENABLED(CONFIG_ARM64_SSBD)) {

		pr_info_once("SSBD disabled by kernel configuration\n");

		return;

	}



	if (this_cpu_has_cap(ARM64_SSBS)) {

		if (state)

			asm volatile(SET_PSTATE_SSBS(0));
@@ -467,7 +471,6 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, 


	return required;

}

#endif	/* CONFIG_ARM64_SSBD */



static void __maybe_unused

cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
@@ -759,14 +762,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors),

	},

#endif

#ifdef CONFIG_ARM64_SSBD

	{

		.desc = "Speculative Store Bypass Disable",

		.capability = ARM64_SSBD,

		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

		.matches = has_ssbd_mitigation,

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1188873

	{

		/* Cortex-A76 r0p0 to r2p0 */