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Commit d3f32dc2 authored by Kevin Groeneveld's avatar Kevin Groeneveld Committed by Greg Kroah-Hartman
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spi: spi-imx: fix MX51_ECSPI_* macros when cs > 3 



[ Upstream commit 87c614175bbf28d3fd076dc2d166bac759e41427 ]

When using gpio based chip select the cs value can go outside the range
0 – 3. The various MX51_ECSPI_* macros did not take this into consideration
resulting in possible corruption of the configuration.

For example for any cs value over 3 the SCLKPHA bits would not be set and
other values in the register possibly corrupted.

One way to fix this is to just mask the cs bits to 2 bits. This still
allows all 4 native chip selects to work as well as gpio chip selects
(which can use any of the 4 chip select configurations).

Signed-off-by: default avatarKevin Groeneveld <kgroeneveld@lenbrook.com>
Link: https://lore.kernel.org/r/20230318222132.3373-1-kgroeneveld@lenbrook.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent bf80dbd5

drivers/spi/spi-imx.c

+18 −6
Original line number Diff line number Diff line
@@ -239,6 +239,18 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, 
	return true;

}



/*

 * Note the number of natively supported chip selects for MX51 is 4. Some

 * devices may have less actual SS pins but the register map supports 4. When

 * using gpio chip selects the cs values passed into the macros below can go

 * outside the range 0 - 3. We therefore need to limit the cs value to avoid

 * corrupting bits outside the allocated locations.

 *

 * The simplest way to do this is to just mask the cs bits to 2 bits. This

 * still allows all 4 native chip selects to work as well as gpio chip selects

 * (which can use any of the 4 chip select configurations).

 */



#define MX51_ECSPI_CTRL		0x08

#define MX51_ECSPI_CTRL_ENABLE		(1 <<  0)

#define MX51_ECSPI_CTRL_XCH		(1 <<  2)
@@ -247,16 +259,16 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, 
#define MX51_ECSPI_CTRL_DRCTL(drctl)	((drctl) << 16)

#define MX51_ECSPI_CTRL_POSTDIV_OFFSET	8

#define MX51_ECSPI_CTRL_PREDIV_OFFSET	12

#define MX51_ECSPI_CTRL_CS(cs)		((cs) << 18)

#define MX51_ECSPI_CTRL_CS(cs)		((cs & 3) << 18)

#define MX51_ECSPI_CTRL_BL_OFFSET	20

#define MX51_ECSPI_CTRL_BL_MASK		(0xfff << 20)



#define MX51_ECSPI_CONFIG	0x0c

#define MX51_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs) +  0))

#define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs) +  4))

#define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs) +  8))

#define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs) + 12))

#define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs) + 20))

#define MX51_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs & 3) +  0))

#define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs & 3) +  4))

#define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs & 3) +  8))

#define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs & 3) + 12))

#define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs & 3) + 20))



#define MX51_ECSPI_INT		0x10

#define MX51_ECSPI_INT_TEEN		(1 <<  0)