Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d387ac13 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2018-12-07' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "There's a bit more in here than I'd like, and I'm hoping things calm
  down when I'm out.

  msm:
   - a bunch of display fixes for the new DPU
   - a couple of command submission fixes

  omap:
   - some DSI fixes

  ast:
   - driver unload crash fix

  core:
   - fix the lease uevent so userspace can distinguish it

  amd:
   - fix a bpc regression
   - fix lru handling regression
   - fixed firmware support for new GPUs
   - power management fixes for vega20"

* tag 'drm-fixes-2018-12-07' of git://anongit.freedesktop.org/drm/drm: (37 commits)
  drm/ast: Fix connector leak during driver unload
  drm/amdgpu/vcn: Update vcn.cur_state during suspend
  drm/amd/display: Fix overflow/truncation from strncpy.
  drm/amd/powerplay: improve OD code robustness
  drm/amdgpu: enlarge maximum waiting time of KIQ
  drm/fb-helper: Fix typo in parameter description
  drm/amd/powerplay: support SoftMin/Max setting for some specific DPM
  drm/amd/powerplay: issue pre-display settings for display change event
  drm/amd/powerplay: support new pptable upload on Vega20
  drm/amdgpu/gmc8: always load MC firmware in the driver
  drm/amdgpu/gmc8: update MC firmware for polaris
  drm/amdgpu: update mc firmware image for polaris12 variants
  drm/msm: Fix error return checking
  drm/msm/dpu: Ignore alpha for XBGR8888 format
  drm/msm: dpu: Fix "WARNING: invalid free of devm_ allocated data"
  drm/msm/hdmi: Drop pointless static qualifier in msm_hdmi_bind()
  drm/msm: Move fence put to where failure occurs
  drm/msm: dpu: Don't set legacy plane->crtc pointer
  drm/msm/gpu: Don't map command buffers with nr_relocs equal to 0
  drm/msm/hdmi: Enable HPD after HDMI IRQ is set up
  ...
parents 7f80c732 e594a5e3

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −1
Original line number Diff line number Diff line
@@ -233,7 +233,7 @@ enum amdgpu_kiq_irq { 


#define MAX_KIQ_REG_WAIT       5000 /* in usecs, 5ms */

#define MAX_KIQ_REG_BAILOUT_INTERVAL   5 /* in msecs, 5ms */

#define MAX_KIQ_REG_TRY 20

#define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */



int amdgpu_device_ip_set_clockgating_state(void *dev,

					   enum amd_ip_block_type block_type,

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

+1 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = { 
	[AMDGPU_HW_IP_UVD_ENC]	=	1,

	[AMDGPU_HW_IP_VCN_DEC]	=	1,

	[AMDGPU_HW_IP_VCN_ENC]	=	1,

	[AMDGPU_HW_IP_VCN_JPEG]	=	1,

};



static int amdgput_ctx_total_num_entities(void)

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+3 −3
Original line number Diff line number Diff line
@@ -467,9 +467,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 
	if (!info->return_size || !info->return_pointer)

		return -EINVAL;



	/* Ensure IB tests are run on ring */

	flush_delayed_work(&adev->late_init_work);



	switch (info->query) {

	case AMDGPU_INFO_ACCEL_WORKING:

		ui32 = adev->accel_working;
@@ -950,6 +947,9 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 
	struct amdgpu_fpriv *fpriv;

	int r, pasid;



	/* Ensure IB tests are run on ring */

	flush_delayed_work(&adev->late_init_work);



	file_priv->driver_priv = NULL;



	r = pm_runtime_get_sync(dev->dev);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

+33 −11
Original line number Diff line number Diff line
@@ -56,6 +56,9 @@ MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 
MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");

MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");

MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");

MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin");

MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin");

MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin");



static const u32 golden_settings_tonga_a11[] =

{
@@ -224,12 +227,38 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 
		chip_name = "tonga";

		break;

	case CHIP_POLARIS11:

		if (((adev->pdev->device == 0x67ef) &&

		     ((adev->pdev->revision == 0xe0) ||

		      (adev->pdev->revision == 0xe5))) ||

		    ((adev->pdev->device == 0x67ff) &&

		     ((adev->pdev->revision == 0xcf) ||

		      (adev->pdev->revision == 0xef) ||

		      (adev->pdev->revision == 0xff))))

			chip_name = "polaris11_k";

		else if ((adev->pdev->device == 0x67ef) &&

			 (adev->pdev->revision == 0xe2))

			chip_name = "polaris11_k";

		else

			chip_name = "polaris11";

		break;

	case CHIP_POLARIS10:

		if ((adev->pdev->device == 0x67df) &&

		    ((adev->pdev->revision == 0xe1) ||

		     (adev->pdev->revision == 0xf7)))

			chip_name = "polaris10_k";

		else

			chip_name = "polaris10";

		break;

	case CHIP_POLARIS12:

		if (((adev->pdev->device == 0x6987) &&

		     ((adev->pdev->revision == 0xc0) ||

		      (adev->pdev->revision == 0xc3))) ||

		    ((adev->pdev->device == 0x6981) &&

		     ((adev->pdev->revision == 0x00) ||

		      (adev->pdev->revision == 0x01) ||

		      (adev->pdev->revision == 0x10))))

			chip_name = "polaris12_k";

		else

			chip_name = "polaris12";

		break;

	case CHIP_FIJI:
@@ -337,7 +366,7 @@ static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) 
	const struct mc_firmware_header_v1_0 *hdr;

	const __le32 *fw_data = NULL;

	const __le32 *io_mc_regs = NULL;

	u32 data, vbios_version;

	u32 data;

	int i, ucode_size, regs_size;



	/* Skip MC ucode loading on SR-IOV capable boards.
@@ -348,13 +377,6 @@ static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) 
	if (amdgpu_sriov_bios(adev))

		return 0;



	WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);

	data = RREG32(mmMC_SEQ_IO_DEBUG_DATA);

	vbios_version = data & 0xf;



	if (vbios_version == 0)

		return 0;



	if (!adev->gmc.fw)

		return -EINVAL;

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

+2 −1
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); 
static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);

static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);

static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr);

static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);



/**

 * vcn_v1_0_early_init - set function pointers
@@ -222,7 +223,7 @@ static int vcn_v1_0_hw_fini(void *handle) 
	struct amdgpu_ring *ring = &adev->vcn.ring_dec;



	if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))

		vcn_v1_0_stop(adev);

		vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);



	ring->ready = false;