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Commit d37cf5f7 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Daniel Vetter
Browse files

drm/i915/bdw: Cleanup pre prod workarounds 

as these have been fixed in production hw and hurt performance
if applied.

v2: adjust requested ring space (Ville)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83482


Tested-by: default avatarzhoujian <jianx.zhou@intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent bda0381e

drivers/gpu/drm/i915/intel_ringbuffer.c

+2 −13
Original line number Diff line number Diff line
@@ -707,7 +707,7 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) 
	 * update the number of dwords required based on the

	 * actual number of workarounds applied

	 */

	ret = intel_ring_begin(ring, 24);

	ret = intel_ring_begin(ring, 18);

	if (ret)

		return ret;
@@ -722,19 +722,8 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) 
	intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,

			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));



	/*

	 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for

	 * pre-production hardware

	 */

	intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,

			   _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS

					      | GEN8_SAMPLER_POWER_BYPASS_DIS));



	intel_ring_emit_wa(ring, GEN7_HALF_SLICE_CHICKEN1,

			   _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));



	intel_ring_emit_wa(ring, COMMON_SLICE_CHICKEN2,

			   _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));

			   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));



	/* Use Force Non-Coherent whenever executing a 3D context. This is a

	 * workaround for for a possible hang in the unlikely event a TLB