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Commit d35e872f authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: alpha-pll: Export required symbols from alpla-pll"

parents b7a4fe50 96bd24d3

drivers/clk/qcom/clk-alpha-pll.c

+2 −0
Original line number Diff line number Diff line
@@ -1118,6 +1118,7 @@ int clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 
							PLL_RESET_N);

	return ret;

}

EXPORT_SYMBOL(clk_trion_pll_configure);



static int clk_trion_pll_is_enabled(struct clk_hw *hw)

{
@@ -3843,6 +3844,7 @@ int clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 


	return 0;

}

EXPORT_SYMBOL(clk_regera_pll_configure);



static int clk_regera_pll_enable(struct clk_hw *hw)

{

drivers/clk/qcom/vdd-level-sm8150.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2020, The Linux Foundation. All rights reserved. */



#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_SM8150_H

#define __DRIVERS_CLK_QCOM_VDD_LEVEL_SM8150_H



#include <linux/regulator/consumer.h>

#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>



enum vdd_levels {

	VDD_NONE,

	VDD_MIN,		/* MIN SVS */

	VDD_LOWER,		/* SVS2 */

	VDD_LOW,		/* SVS */

	VDD_LOW_L1,		/* SVSL1 */

	VDD_NOMINAL,		/* NOM */

	VDD_HIGH,		/* TURBO */

	VDD_HIGH_L1,		/* TURBOL1 */

	VDD_MM_NUM = VDD_HIGH_L1,

	VDD_NUM,

};



static int vdd_corner[] = {

	[VDD_NONE]    = 0,

	[VDD_MIN]     = RPMH_REGULATOR_LEVEL_MIN_SVS,

	[VDD_LOWER]   = RPMH_REGULATOR_LEVEL_LOW_SVS,

	[VDD_LOW]     = RPMH_REGULATOR_LEVEL_SVS,

	[VDD_LOW_L1]  = RPMH_REGULATOR_LEVEL_SVS_L1,

	[VDD_NOMINAL] = RPMH_REGULATOR_LEVEL_NOM,

	[VDD_HIGH]    = RPMH_REGULATOR_LEVEL_TURBO,

	[VDD_HIGH_L1] = RPMH_REGULATOR_LEVEL_TURBO_L1,

};



#endif

drivers/mailbox/qcom-apcs-ipc-mailbox.c

+1 −0
Original line number Diff line number Diff line
@@ -130,6 +130,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { 
	{ .compatible = "qcom,sdxlemur-apcs-gcc", .data = (void *)8 },

	{ .compatible = "qcom,scuba-apcs-hmss-global", .data = (void *)8 },

	{ .compatible = "qcom,monaco-apcs-hmss-global", .data = (void *)8 },

	{ .compatible = "qcom,sm8150-spcs-global", .data = (void *)0 },

	{}

};

MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);

include/dt-bindings/clock/qcom,camcc-sm8150.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8150_H

#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8150_H



/* CAM_CC clocks */

#define CAM_CC_PLL0					0

#define CAM_CC_PLL0_OUT_EVEN				1

#define CAM_CC_PLL0_OUT_ODD				2

#define CAM_CC_PLL1					3

#define CAM_CC_PLL1_OUT_EVEN				4

#define CAM_CC_PLL2					5

#define CAM_CC_PLL2_OUT_MAIN				6

#define CAM_CC_PLL3					7

#define CAM_CC_PLL3_OUT_EVEN				8

#define CAM_CC_PLL4					9

#define CAM_CC_PLL4_OUT_EVEN				10

#define CAM_CC_BPS_AHB_CLK				11

#define CAM_CC_BPS_AREG_CLK				12

#define CAM_CC_BPS_AXI_CLK				13

#define CAM_CC_BPS_CLK					14

#define CAM_CC_BPS_CLK_SRC				15

#define CAM_CC_CAMNOC_AXI_CLK				16

#define CAM_CC_CAMNOC_AXI_CLK_SRC			17

#define CAM_CC_CAMNOC_DCD_XO_CLK			18

#define CAM_CC_CCI_0_CLK				19

#define CAM_CC_CCI_0_CLK_SRC				20

#define CAM_CC_CCI_1_CLK				21

#define CAM_CC_CCI_1_CLK_SRC				22

#define CAM_CC_CORE_AHB_CLK				23

#define CAM_CC_CPAS_AHB_CLK				24

#define CAM_CC_CPHY_RX_CLK_SRC				25

#define CAM_CC_CSI0PHYTIMER_CLK				26

#define CAM_CC_CSI0PHYTIMER_CLK_SRC			27

#define CAM_CC_CSI1PHYTIMER_CLK				28

#define CAM_CC_CSI1PHYTIMER_CLK_SRC			29

#define CAM_CC_CSI2PHYTIMER_CLK				30

#define CAM_CC_CSI2PHYTIMER_CLK_SRC			31

#define CAM_CC_CSI3PHYTIMER_CLK				32

#define CAM_CC_CSI3PHYTIMER_CLK_SRC			33

#define CAM_CC_CSIPHY0_CLK				34

#define CAM_CC_CSIPHY1_CLK				35

#define CAM_CC_CSIPHY2_CLK				36

#define CAM_CC_CSIPHY3_CLK				37

#define CAM_CC_FAST_AHB_CLK_SRC				38

#define CAM_CC_FD_CORE_CLK				39

#define CAM_CC_FD_CORE_CLK_SRC				40

#define CAM_CC_FD_CORE_UAR_CLK				41

#define CAM_CC_GDSC_CLK					42

#define CAM_CC_ICP_AHB_CLK				43

#define CAM_CC_ICP_CLK					44

#define CAM_CC_ICP_CLK_SRC				45

#define CAM_CC_IFE_0_AXI_CLK				46

#define CAM_CC_IFE_0_CLK				47

#define CAM_CC_IFE_0_CLK_SRC				48

#define CAM_CC_IFE_0_CPHY_RX_CLK			49

#define CAM_CC_IFE_0_CSID_CLK				50

#define CAM_CC_IFE_0_CSID_CLK_SRC			51

#define CAM_CC_IFE_0_DSP_CLK				52

#define CAM_CC_IFE_1_AXI_CLK				53

#define CAM_CC_IFE_1_CLK				54

#define CAM_CC_IFE_1_CLK_SRC				55

#define CAM_CC_IFE_1_CPHY_RX_CLK			56

#define CAM_CC_IFE_1_CSID_CLK				57

#define CAM_CC_IFE_1_CSID_CLK_SRC			58

#define CAM_CC_IFE_1_DSP_CLK				59

#define CAM_CC_IFE_LITE_0_CLK				60

#define CAM_CC_IFE_LITE_0_CLK_SRC			61

#define CAM_CC_IFE_LITE_0_CPHY_RX_CLK			62

#define CAM_CC_IFE_LITE_0_CSID_CLK			63

#define CAM_CC_IFE_LITE_0_CSID_CLK_SRC			64

#define CAM_CC_IFE_LITE_1_CLK				65

#define CAM_CC_IFE_LITE_1_CLK_SRC			66

#define CAM_CC_IFE_LITE_1_CPHY_RX_CLK			67

#define CAM_CC_IFE_LITE_1_CSID_CLK			68

#define CAM_CC_IFE_LITE_1_CSID_CLK_SRC			69

#define CAM_CC_IPE_0_AHB_CLK				70

#define CAM_CC_IPE_0_AREG_CLK				71

#define CAM_CC_IPE_0_AXI_CLK				72

#define CAM_CC_IPE_0_CLK				73

#define CAM_CC_IPE_0_CLK_SRC				74

#define CAM_CC_IPE_1_AHB_CLK				75

#define CAM_CC_IPE_1_AREG_CLK				76

#define CAM_CC_IPE_1_AXI_CLK				77

#define CAM_CC_IPE_1_CLK				78

#define CAM_CC_JPEG_CLK					79

#define CAM_CC_JPEG_CLK_SRC				80

#define CAM_CC_LRME_CLK					81

#define CAM_CC_LRME_CLK_SRC				82

#define CAM_CC_MCLK0_CLK				83

#define CAM_CC_MCLK0_CLK_SRC				84

#define CAM_CC_MCLK1_CLK				85

#define CAM_CC_MCLK1_CLK_SRC				86

#define CAM_CC_MCLK2_CLK				87

#define CAM_CC_MCLK2_CLK_SRC				88

#define CAM_CC_MCLK3_CLK				89

#define CAM_CC_MCLK3_CLK_SRC				90

#define CAM_CC_SLOW_AHB_CLK_SRC				91



/* CAM_CC power domains */

#define BPS_GDSC					0

#define IFE_0_GDSC					1

#define IFE_1_GDSC					2

#define IPE_0_GDSC					3

#define IPE_1_GDSC					4

#define TITAN_TOP_GDSC					5



/* CAM_CC resets */

#define CAM_CC_BPS_BCR					0

#define CAM_CC_CAMNOC_BCR				1

#define CAM_CC_CCI_BCR					2

#define CAM_CC_CPAS_BCR					3

#define CAM_CC_CSI0PHY_BCR				4

#define CAM_CC_CSI1PHY_BCR				5

#define CAM_CC_CSI2PHY_BCR				6

#define CAM_CC_CSI3PHY_BCR				7

#define CAM_CC_FD_BCR					8

#define CAM_CC_ICP_BCR					9

#define CAM_CC_IFE_0_BCR				10

#define CAM_CC_IFE_1_BCR				11

#define CAM_CC_IFE_LITE_0_BCR				12

#define CAM_CC_IFE_LITE_1_BCR				13

#define CAM_CC_IPE_0_BCR				14

#define CAM_CC_IPE_1_BCR				15

#define CAM_CC_JPEG_BCR					16

#define CAM_CC_LRME_BCR					17

#define CAM_CC_MCLK0_BCR				18

#define CAM_CC_MCLK1_BCR				19

#define CAM_CC_MCLK2_BCR				20

#define CAM_CC_MCLK3_BCR				21



#endif

include/dt-bindings/clock/qcom,dispcc-sm8150.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8150_H

#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8150_H



/* DISP_CC clocks */

#define DISP_CC_PLL0					0

#define DISP_CC_PLL1					1

#define DISP_CC_MDSS_AHB_CLK				2

#define DISP_CC_MDSS_AHB_CLK_SRC			3

#define DISP_CC_MDSS_BYTE0_CLK				4

#define DISP_CC_MDSS_BYTE0_CLK_SRC			5

#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC			6

#define DISP_CC_MDSS_BYTE0_INTF_CLK			7

#define DISP_CC_MDSS_BYTE1_CLK				8

#define DISP_CC_MDSS_BYTE1_CLK_SRC			9

#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC			10

#define DISP_CC_MDSS_BYTE1_INTF_CLK			11

#define DISP_CC_MDSS_DP_AUX1_CLK			12

#define DISP_CC_MDSS_DP_AUX1_CLK_SRC			13

#define DISP_CC_MDSS_DP_AUX_CLK				14

#define DISP_CC_MDSS_DP_AUX_CLK_SRC			15

#define DISP_CC_MDSS_DP_CRYPTO1_CLK			16

#define DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC			17

#define DISP_CC_MDSS_DP_CRYPTO_CLK			18

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC			19

#define DISP_CC_MDSS_DP_LINK1_CLK			20

#define DISP_CC_MDSS_DP_LINK1_CLK_SRC			21

#define DISP_CC_MDSS_DP_LINK1_INTF_CLK			22

#define DISP_CC_MDSS_DP_LINK_CLK			23

#define DISP_CC_MDSS_DP_LINK_CLK_SRC			24

#define DISP_CC_MDSS_DP_LINK_INTF_CLK			25

#define DISP_CC_MDSS_DP_PIXEL1_CLK			26

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC			27

#define DISP_CC_MDSS_DP_PIXEL2_CLK			28

#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC			29

#define DISP_CC_MDSS_DP_PIXEL_CLK			30

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC			31

#define DISP_CC_MDSS_EDP_AUX_CLK			32

#define DISP_CC_MDSS_EDP_AUX_CLK_SRC			33

#define DISP_CC_MDSS_EDP_GTC_CLK			34

#define DISP_CC_MDSS_EDP_GTC_CLK_SRC			35

#define DISP_CC_MDSS_EDP_LINK_CLK			36

#define DISP_CC_MDSS_EDP_LINK_CLK_SRC			37

#define DISP_CC_MDSS_EDP_LINK_INTF_CLK			38

#define DISP_CC_MDSS_EDP_PIXEL_CLK			39

#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC			40

#define DISP_CC_MDSS_ESC0_CLK				41

#define DISP_CC_MDSS_ESC0_CLK_SRC			42

#define DISP_CC_MDSS_ESC1_CLK				43

#define DISP_CC_MDSS_ESC1_CLK_SRC			44

#define DISP_CC_MDSS_MDP_CLK				45

#define DISP_CC_MDSS_MDP_CLK_SRC			46

#define DISP_CC_MDSS_MDP_LUT_CLK			47

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK			48

#define DISP_CC_MDSS_PCLK0_CLK				49

#define DISP_CC_MDSS_PCLK0_CLK_SRC			50

#define DISP_CC_MDSS_PCLK1_CLK				51

#define DISP_CC_MDSS_PCLK1_CLK_SRC			52

#define DISP_CC_MDSS_ROT_CLK				53

#define DISP_CC_MDSS_ROT_CLK_SRC			54

#define DISP_CC_MDSS_RSCC_AHB_CLK			55

#define DISP_CC_MDSS_RSCC_VSYNC_CLK			56

#define DISP_CC_MDSS_VSYNC_CLK				57

#define DISP_CC_MDSS_VSYNC_CLK_SRC			58

#define DISP_CC_XO_CLK					59



/* DISP_CC power domains */

#define MDSS_CORE_GDSC					0



/* DISP_CC resets */

#define DISP_CC_MDSS_CORE_BCR				0

#define DISP_CC_MDSS_RSCC_BCR				1

#define DISP_CC_MDSS_SPDM_BCR				2



#endif