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Commit d32ac731 authored by Dhaval Patel's avatar Dhaval Patel Committed by Jayaprakash Madisetty
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disp: msm: sde: disable vsync counter before tear check update 



Disable vsync counter before single buffer tear check
update. It allows to trigger the resolution switch
frame as posted start frame.

Change-Id: I2726372fd0e6d14ab0f79e3e3b0731a074158682
Signed-off-by: default avatarDhaval Patel <quic_pdhaval@quicinc.com>
Signed-off-by: default avatarJayaprakash Madisetty <quic_jmadiset@quicinc.com>
parent d55329a4

msm/sde/sde_hw_intf.c

+5 −2
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.

 */

#include <linux/iopoll.h>
@@ -543,20 +544,20 @@ static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf, 
		struct sde_hw_tear_check *te)

{

	struct sde_hw_blk_reg_map *c;

	int cfg;

	u32 cfg = 0;



	if (!intf)

		return -EINVAL;



	c = &intf->hw;



	cfg = BIT(19); /* VSYNC_COUNTER_EN */

	if (te->hw_vsync_mode)

		cfg |= BIT(20);



	cfg |= te->vsync_count;



	SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);

	wmb(); /* disable vsync counter before updating single buffer registers */

	SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);

	SDE_REG_WRITE(c, INTF_TEAR_VSYNC_INIT_VAL, te->vsync_init_val);

	SDE_REG_WRITE(c, INTF_TEAR_RD_PTR_IRQ, te->rd_ptr_irq);
@@ -567,6 +568,8 @@ static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf, 
			 te->sync_threshold_start));

	SDE_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT,

			(te->start_pos + te->sync_threshold_start + 1));

	cfg |= BIT(19); /* VSYNC_COUNTER_EN */

	SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);



	return 0;

}