Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d30e413f authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'phy-for-5.2' of... 

Merge tag 'phy-for-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy

 into usb-next

Kishon writes:

phy: for 5.2

  *) Add a new *release* phy_ops invoked when the consumer relinquishes PHY
     that can be used to undo the operation performed in xlate
  *) Add new driver to support USB2 PHY and shared USB3 + PCIE PHY in Amlogic
     G12A SoC Family.
  *) Add new driver to support for Broadcom's Stingray USB PHY (Type 1 has
     one super speed PHY and one high speed PHY, Type 2 has one high speed PHY)
  *) Add new driver to support USB PHY in hi3660 SoC of Hisilicon
  *) Add new driver to support UFS M-PHY in MediaTek SoC
  *) Add new driver to support XUSB pad controller in Tegra186 SoCs
  *) Add new driver to support SERDES in TI's AM654 platform
  *) Add support for generation 2 USB2 PHY and gneration 3 USB2 PHY in r8a77470
     to phy-rcar-gen2.c and phy-rcar-gen3-usb2.c respectively
  *) Add support for PCIe QMP PHY support in msm8998 to phy-qcom-qmp.c
  *) Add support for SERDES6G in phy-ocelot-serdes.c
  *) Add support to set drive impedance from device tree in phy-rockchip-emmc.c
  *) Add support to power up/down the VBUS voltage rail in phy-fsl-imx8mq-usb.c
  *) Add support to shut off regulators that power UFS during system suspend
  *) Re-design phy-rcar-gen3-usb2.c to create separate PHY instances for each
     channel which helps to enable/disable interrupts for each instance
     independently
  *) Fix PCIe power up sequence to follow the TRM in order to ensure the DPLL &
     PHY operates correctly over the entire temperature range.
  *) Use devm_clk_get_optional to get optional clocks instead of adding
     custom error checks

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>

* tag 'phy-for-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (51 commits)
  dt-bindings: phy-qcom-qmp: Tweak qcom,msm8998-qmp-ufs-phy
  dt-bindings: phy-qcom-qmp: Add qcom,msm8998-qmp-pcie-phy
  phy: Add usb phy support for hi3660 Soc of Hisilicon
  dt-bindings: phy: Add support for HiSilicon's hi3660 USB PHY
  scsi: phy: mediatek: fix typo in author's email address
  phy: ocelot-serdes: Add support for SERDES6G muxing
  phy: fsl-imx8mq-usb: add support for VBUS power control
  dt-bindings: phy-imx8mq-usb: add optional vbus supply regulator
  phy: qcom-qmp: Add msm8998 PCIe QMP PHY support
  phy: ti: am654-serdes: Support all clksel values
  phy: ti: Add a new SERDES driver for TI's AM654x SoC
  dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoC
  phy: core: Invoke pm_runtime_get_*/pm_runtime_put_* before invoking reset callback
  phy: core: Add *release* phy_ops invoked when the consumer relinquishes PHY
  phy: phy-meson-gxl-usb2: get optional clock by devm_clk_get_optional()
  phy: socionext: get optional clock by devm_clk_get_optional()
  phy: qcom-qusb2: get optional clock by devm_clk_get_optional()
  phy: phy-mtk-tphy: get optional clock by devm_clk_get_optional()
  phy: renesas: rcar-gen3-usb2: enable/disable independent irqs
  phy: renesas: rcar-gen3-usb2: Use pdev's device pointer on dev_vdbg()
  ...
parents 1567d661 70831071

Documentation/devicetree/bindings/phy/brcm,stingray-usb-phy.txt

0 → 100644
+32 −0
Original line number Diff line number Diff line 
Broadcom Stingray USB PHY



Required properties:

 - compatible : should be one of the listed compatibles

	- "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.

	- "brcm,sr-usb-hs-phy" is a single HS PHY.

 - reg: offset and length of the PHY blocks registers

 - #phy-cells:

   - Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate

     the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.

   - Must be 0 for brcm,sr-usb-hs-phy.



Refer to phy/phy-bindings.txt for the generic PHY binding properties



Example:

	usbphy0: usb-phy@0 {

		compatible = "brcm,sr-usb-combo-phy";

		reg = <0x00000000 0x100>;

		#phy-cells = <1>;

	};



	usbphy1: usb-phy@10000 {

		compatible = "brcm,sr-usb-combo-phy";

		reg = <0x00010000 0x100>,

		#phy-cells = <1>;

	};



	usbphy2: usb-phy@20000 {

		compatible = "brcm,sr-usb-hs-phy";

		reg = <0x00020000 0x100>,

		#phy-cells = <0>;

	};

Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt

+3 −0
Original line number Diff line number Diff line
@@ -7,6 +7,9 @@ Required properties: 
- clocks:	phandles to the clocks for each clock listed in clock-names

- clock-names:	must contain "phy"



Optional properties:

- vbus-supply: A phandle to the regulator for USB VBUS.



Example:

	usb3_phy0: phy@381f0040 {

		compatible = "fsl,imx8mq-usb-phy";

Documentation/devicetree/bindings/phy/meson-g12a-usb2-phy.txt

0 → 100644
+22 −0
Original line number Diff line number Diff line 
* Amlogic G12A USB2 PHY binding



Required properties:

- compatible:	Should be "amlogic,meson-g12a-usb2-phy"

- reg:		The base address and length of the registers

- #phys-cells:	must be 0 (see phy-bindings.txt in this directory)

- clocks:	a phandle to the clock of this PHY

- clock-names:	must be "xtal"

- resets:	a phandle to the reset line of this PHY

- reset-names:	must be "phy"

- phy-supply:	see phy-bindings.txt in this directory



Example:

	usb2_phy0: phy@36000 {

		compatible = "amlogic,g12a-usb2-phy";

		reg = <0x0 0x36000 0x0 0x2000>;

		clocks = <&xtal>;

		clock-names = "xtal";

		resets = <&reset RESET_USB_PHY21>;

		reset-names = "phy";

		#phy-cells = <0>;

	};

Documentation/devicetree/bindings/phy/meson-g12a-usb3-pcie-phy.txt

0 → 100644
+22 −0
Original line number Diff line number Diff line 
* Amlogic G12A USB3 + PCIE Combo PHY binding



Required properties:

- compatible:	Should be "amlogic,meson-g12a-usb3-pcie-phy"

- #phys-cells:	must be 1. The cell number is used to select the phy mode

  as defined in <dt-bindings/phy/phy.h> between PHY_TYPE_USB3 and PHY_TYPE_PCIE

- reg:		The base address and length of the registers

- clocks:	a phandle to the 100MHz reference clock of this PHY

- clock-names:	must be "ref_clk"

- resets:	phandle to the reset lines for the PHY control

- reset-names:	must be "phy"



Example:

	usb3_pcie_phy: phy@46000 {

		compatible = "amlogic,g12a-usb3-pcie-phy";

		reg = <0x0 0x46000 0x0 0x2000>;

		clocks = <&clkc CLKID_PCIE_PLL>;

		clock-names = "ref_clk";

		resets = <&reset RESET_PCIE_PHY>;

		reset-names = "phy";

		#phy-cells = <1>;

	};

Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt

+9 −0
Original line number Diff line number Diff line
@@ -36,11 +36,20 @@ Required properties: 
  - Tegra124: "nvidia,tegra124-xusb-padctl"

  - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"

  - Tegra210: "nvidia,tegra210-xusb-padctl"

  - Tegra186: "nvidia,tegra186-xusb-padctl"

- reg: Physical base address and length of the controller's registers.

- resets: Must contain an entry for each entry in reset-names.

- reset-names: Must include the following entries:

  - "padctl"



For Tegra186:

- avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY

  power supply. Must supply 1.8 V.

- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply

  3.3 V.

- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.

- vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.





Pad nodes:

==========