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Commit d2c77083 authored by Venkata Narendra Kumar Gutta's avatar Venkata Narendra Kumar Gutta Committed by Elliot Berman
Browse files

arm64: dts: qcom: Add secondary VM dts file for lahaina 

Add secondary VM devicetree file for lahaina chipset. This file
adds the basic nodes like CPU, intc, hypervisor that are required
for the VM.

Change-Id: Ice6fb0b6160fa27853fac6076f3d965c3463528e
parent 6adebd3e

qcom/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -18,6 +18,8 @@ dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \ 
	lahaina-qrd-module.dtb

endif



dtb-$(CONFIG_ARCH_QTI_VM) += lahaina-svm1.dtb



always		:= $(dtb-y)

subdir-y	:= $(dts-dirs)

clean-files	:= *.dtb *.dtbo

qcom/lahaina-svm1.dts

0 → 100644
+7 −0
Original line number Diff line number Diff line 
/dts-v1/;



#include "lahaina-svm1.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. Secondary Virtual Machine";

};

qcom/lahaina-svm1.dtsi

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+85 −0
Original line number Diff line number Diff line 
#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	#address-cells = <0x2>;

	#size-cells = <0x2>;

	interrupt-parent = <&vgic>;



	chosen {

	};



	cpus {

		#address-cells = <0x2>;

		#size-cells = <0x0>;



		CPU0: cpu@0 {

			compatible = "arm,armv8";

			reg = <0x0 0x0>;

			device_type = "cpu";

			enable-method = "psci";

			cpu-idle-states = <0x2>;

		};

	};



	vgic: interrupt-controller {

		compatible = "arm,gic-v3";

		interrupt-controller;

		#interrupt-cells = <0x3>;

		reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */

		      <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	qcom,vm-config {

		compatible = "qcom,vm-1.0";

		vm-type = "aarch64-guest";

		boot-config = "fdt,unified";

		os-type = "linux";

		kernel-entry-segment = "kernel";

		kernel-entry-offset = <0x0 0x0>;

		vendor = "Qualcomm";

		image-name = "qcom,trustedvm";

		qcom,pasid = <0x0 0x1c>;



		memory {

			#address-cells = <0x2>;

			#size-cells = <0x0>;

			base-address = <0x0 0xD0800000>;

			size-min = <0x0 0x8000000>;    /* 128 MB */

		};



		segments {

				/* offset and size */

			kernel = <0x0 0x8000 0x0 0x2000000>;  /* 32 MB */

			dt = <0x0 0x7000000 0x0 0x4000>;      /* 16 KB */

		};



		vcpus {

			config = "/cpus";

			affinity = "static";

			affinity-map = <0x0>;   /* VCPU -> CPU */

		};



		interrupts {

			config = &vgic;

		};



		vdevices {

			peer-default;

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		always-on;

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;

		interrupt-parent = <&vgic>;

	};

};