disp: msm: sde: populate WB display encoder list before dsi

This changes swaps the order of encode initialization between
wb and dsi displays. This ensures that wb encoder is registered
before DSI/DP encoder in mode_list and it allows single CRTC
to loop through WB encoder before other encoder during mirror mode
topology like CWB use case. With existing order of encoder list, CWB
flush is happening after primary commit flush which is causing cwb
failures when there is a cpu latency.

Change-Id: I24d6b4f27271d46e9743d17a624ac7e0930f7474
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>