Merge "dt-bindings: clocks: Add gpu cc clock controller bindings for Lahaina"

Qualcomm Graphics Clock & Reset Controller Binding

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Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding

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Required properties :

- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc"

- reg : shall contain base register location and length

- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc",

		"qcom,lahaina-gpucc.

- reg: shall contain base register offset and size.

- reg-names: names of registers listed in the same order as in the reg property.

		Must contain "cc_base".

- #clock-cells : from common clock binding, shall contain 1

- #reset-cells : from common reset binding, shall contain 1

Optional properties :

- #power-domain-cells : from generic power domain binding, shall contain 1

- clocks : shall contain the XO clock

	   shall contain the gpll0 out main clock (msm8998)

		shall be "gpll0" (msm8998)

Example:

1.

	gpucc: clock-controller@5090000 {

		compatible = "qcom,sdm845-gpucc";

		reg = <0x5090000 0x9000>;

		clocks = <&rpmhcc RPMH_CXO_CLK>;

		clock-names = "xo";

	};

2.

	clock_gpucc: clock-controller@3d90000 {

		compatible = "qcom,lahaina-gpucc";

		reg = <0x3d90000 0x9000>;

		reg-names = "cc_base";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};