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Commit d267d851 authored by Andy Walls's avatar Andy Walls Committed by Mauro Carvalho Chehab
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V4L/DVB (9110): cx18: Add default behavior of checking and retrying PCI MMIO accesses



cx18: Add default behavior of checking and retrying PCI MMIO accesses.
The concept of checking and retrying PCI MMIO accesses for better reliability
in older motherboards was suggested by Steve Toth <stoth@linuxtv.org>.  This
change implements MMIO retries and the retry_mmio module parameter that is
enabled by default.  Limited experiments have shown this is more reliable than
the mmio_ndelay parameter.  mmio_ndelay has insignificant effect with retries
enabled.

Signed-off-by: default avatarAndy Walls <awalls@radix.net>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent 7f987678
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+11 −0
Original line number Diff line number Diff line
@@ -42,6 +42,12 @@ int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value)
	return 0;
}

int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value)
{
	cx18_write_reg_noretry(cx, value, 0xc40000 + addr);
	return 0;
}

u8 cx18_av_read(struct cx18 *cx, u16 addr)
{
	u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3));
@@ -55,6 +61,11 @@ u32 cx18_av_read4(struct cx18 *cx, u16 addr)
	return cx18_read_reg(cx, 0xc40000 + addr);
}

u32 cx18_av_read4_noretry(struct cx18 *cx, u16 addr)
{
	return cx18_read_reg_noretry(cx, 0xc40000 + addr);
}

int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned and_mask,
		   u8 or_value)
{
+2 −0
Original line number Diff line number Diff line
@@ -301,8 +301,10 @@ struct cx18_av_state {
/* cx18_av-core.c 							   */
int cx18_av_write(struct cx18 *cx, u16 addr, u8 value);
int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value);
int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value);
u8 cx18_av_read(struct cx18 *cx, u16 addr);
u32 cx18_av_read4(struct cx18 *cx, u16 addr);
u32 cx18_av_read4_noretry(struct cx18 *cx, u16 addr);
int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value);
int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value);
int cx18_av_cmd(struct cx18 *cx, unsigned int cmd, void *arg);
+12 −6
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ int cx18_av_loadfw(struct cx18 *cx)
		cx18_av_write4(cx, 0x8100, 0x00010000);

		/* Put the 8051 in reset and enable firmware upload */
		cx18_av_write4(cx, CXADEC_DL_CTL, 0x0F000000);
		cx18_av_write4_noretry(cx, CXADEC_DL_CTL, 0x0F000000);

		ptr = fw->data;
		size = fw->size;
@@ -59,22 +59,28 @@ int cx18_av_loadfw(struct cx18 *cx)
			u32 dl_control = 0x0F000000 | i | ((u32)ptr[i] << 16);
			u32 value = 0;
			int retries2;
			int unrec_err = 0;

			for (retries2 = 0; retries2 < 5; retries2++) {
				cx18_av_write4(cx, CXADEC_DL_CTL, dl_control);
			for (retries2 = 0; retries2 < CX18_MAX_MMIO_RETRIES;
			     retries2++) {
				cx18_av_write4_noretry(cx, CXADEC_DL_CTL,
						       dl_control);
				udelay(10);
				value = cx18_av_read4(cx, CXADEC_DL_CTL);
				value = cx18_av_read4_noretry(cx,
							      CXADEC_DL_CTL);
				if (value == dl_control)
					break;
				/* Check if we can correct the byte by changing
				   the address.  We can only write the lower
				   address byte of the address. */
				if ((value & 0x3F00) != (dl_control & 0x3F00)) {
					retries2 = 5;
					unrec_err = 1;
					break;
				}
			}
			if (retries2 >= 5)
			cx18_log_write_retries(cx, retries2,
					cx->reg_mem + 0xc40000 + CXADEC_DL_CTL);
			if (unrec_err || retries2 >= CX18_MAX_MMIO_RETRIES)
				break;
		}
		if (i == size)
+7 −0
Original line number Diff line number Diff line
@@ -96,6 +96,7 @@ static int enc_pcm_buffers = CX18_DEFAULT_ENC_PCM_BUFFERS;

static int cx18_pci_latency = 1;

int cx18_retry_mmio = 1;
int cx18_debug;

module_param_array(tuner, int, &tuner_c, 0644);
@@ -106,6 +107,7 @@ module_param_string(pal, pal, sizeof(pal), 0644);
module_param_string(secam, secam, sizeof(secam), 0644);
module_param_string(ntsc, ntsc, sizeof(ntsc), 0644);
module_param_named(debug, cx18_debug, int, 0644);
module_param_named(retry_mmio, cx18_retry_mmio, int, 0644);
module_param(cx18_pci_latency, int, 0644);
module_param(cx18_first_minor, int, 0644);

@@ -147,6 +149,9 @@ MODULE_PARM_DESC(debug,
MODULE_PARM_DESC(cx18_pci_latency,
		 "Change the PCI latency to 64 if lower: 0 = No, 1 = Yes,\n"
		 "\t\t\tDefault: Yes");
MODULE_PARM_DESC(retry_mmio,
		 "Check and retry memory mapped IO accesses\n"
		 "\t\t\tDefault: 1 [Yes]");
MODULE_PARM_DESC(mmio_ndelay,
		 "Delay (ns) for each CX23418 memory mapped IO access.\n"
		 "\t\t\tTry larger values that are close to a multiple of the\n"
@@ -827,6 +832,7 @@ static int __devinit cx18_probe(struct pci_dev *dev,
	if (retval == 0)
		retval = -ENODEV;
	CX18_ERR("Error %d on initialization\n", retval);
	cx18_log_statistics(cx);

	kfree(cx18_cards[cx18_cards_active]);
	cx18_cards[cx18_cards_active] = NULL;
@@ -931,6 +937,7 @@ static void cx18_remove(struct pci_dev *pci_dev)

	pci_disable_device(cx->dev);

	cx18_log_statistics(cx);
	CX18_INFO("Removed %s, card #%d\n", cx->card_name, cx->num);
}

+11 −0
Original line number Diff line number Diff line
@@ -171,6 +171,7 @@

#define CX18_MAX_PGM_INDEX (400)

extern int cx18_retry_mmio;	/* enable check & retry of mmio accesses */
extern int cx18_debug;


@@ -344,6 +345,13 @@ struct cx18_i2c_algo_callback_data {
	int bus_index;   /* 0 or 1 for the cx23418's 1st or 2nd I2C bus */
};

#define CX18_MAX_MMIO_RETRIES 10

struct cx18_mmio_stats {
	atomic_t retried_write[CX18_MAX_MMIO_RETRIES+1];
	atomic_t retried_read[CX18_MAX_MMIO_RETRIES+1];
};

/* Struct to hold info about cx18 cards */
struct cx18 {
	int num;		/* board number, -1 during init! */
@@ -433,6 +441,9 @@ struct cx18 {
	u32 gpio_val;
	struct mutex gpio_lock;

	/* Statistics */
	struct cx18_mmio_stats mmio_stats;

	/* v4l2 and User settings */

	/* codec settings */
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